Anup Patel 77cf33c171 RISC-V: KVM: Implement guest external interrupt line management ... The RISC-V host will have one guest external interrupt line for each VS-level IMSICs associated with a HART. The guest external interrupt lines are per-HART resources and hypervisor can use HGEIE, HGEIP, and HIE CSRs to manage these guest external interrupt lines. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>		2023-06-18 21:24:33 +05:30
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asm	RISC-V: KVM: Implement guest external interrupt line management	2023-06-18 21:24:33 +05:30
uapi/asm	KVM/riscv changes for 6.4	2023-05-05 06:11:48 -04:00