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78376535c2
Replace spaces with tabs for indentation to fix the checkpatch.pl error ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line Signed-off-by: Juston Li <juston.h.li@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
205 lines
7.2 KiB
C
205 lines
7.2 KiB
C
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#include "ddk750_help.h"
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#include "ddk750_reg.h"
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#include "ddk750_mode.h"
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#include "ddk750_chip.h"
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/*
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SM750LE only:
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This function takes care extra registers and bit fields required to set
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up a mode in SM750LE
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Explanation about Display Control register:
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HW only supports 7 predefined pixel clocks, and clock select is
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in bit 29:27 of Display Control register.
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*/
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static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, unsigned long dispControl)
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{
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unsigned long x, y;
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x = pModeParam->horizontal_display_end;
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y = pModeParam->vertical_display_end;
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/* SM750LE has to set up the top-left and bottom-right
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registers as well.
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Note that normal SM750/SM718 only use those two register for
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auto-centering mode.
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*/
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POKE32(CRT_AUTO_CENTERING_TL,
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FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, TOP, 0)
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| FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, LEFT, 0));
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POKE32(CRT_AUTO_CENTERING_BR,
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FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, BOTTOM, y-1)
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| FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, RIGHT, x-1));
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/* Assume common fields in dispControl have been properly set before
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calling this function.
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This function only sets the extra fields in dispControl.
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*/
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/* Clear bit 29:27 of display control register */
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dispControl &= FIELD_CLEAR(CRT_DISPLAY_CTRL, CLK);
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/* Set bit 29:27 of display control register for the right clock */
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/* Note that SM750LE only need to supported 7 resoluitons. */
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if ( x == 800 && y == 600 )
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL41);
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else if (x == 1024 && y == 768)
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL65);
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else if (x == 1152 && y == 864)
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80);
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else if (x == 1280 && y == 768)
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80);
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else if (x == 1280 && y == 720)
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL74);
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else if (x == 1280 && y == 960)
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108);
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else if (x == 1280 && y == 1024)
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108);
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else /* default to VGA clock */
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL25);
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/* Set bit 25:24 of display controller */
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CRTSELECT, CRT);
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT);
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/* Set bit 14 of display controller */
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dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLOCK_PHASE, ACTIVE_LOW);
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POKE32(CRT_DISPLAY_CTRL, dispControl);
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return dispControl;
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}
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/* only timing related registers will be programed */
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static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
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{
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int ret = 0;
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int cnt = 0;
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unsigned int ulTmpValue, ulReg;
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if(pll->clockType == SECONDARY_PLL)
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{
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/* programe secondary pixel clock */
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POKE32(CRT_PLL_CTRL, formatPllReg(pll));
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POKE32(CRT_HORIZONTAL_TOTAL,
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FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1)
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| FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1));
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POKE32(CRT_HORIZONTAL_SYNC,
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FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width)
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| FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1));
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POKE32(CRT_VERTICAL_TOTAL,
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FIELD_VALUE(0, CRT_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1)
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| FIELD_VALUE(0, CRT_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1));
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POKE32(CRT_VERTICAL_SYNC,
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FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
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| FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
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ulTmpValue = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)|
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FIELD_VALUE(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)|
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FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE)|
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FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE);
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if(getChipType() == SM750LE){
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displayControlAdjust_SM750LE(pModeParam, ulTmpValue);
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}else{
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ulReg = PEEK32(CRT_DISPLAY_CTRL)
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& FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE)
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& FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE)
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& FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING)
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& FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE);
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POKE32(CRT_DISPLAY_CTRL, ulTmpValue|ulReg);
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}
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}
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else if(pll->clockType == PRIMARY_PLL)
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{
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unsigned int ulReservedBits;
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POKE32(PANEL_PLL_CTRL, formatPllReg(pll));
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POKE32(PANEL_HORIZONTAL_TOTAL,
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FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1)
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| FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1));
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POKE32(PANEL_HORIZONTAL_SYNC,
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FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width)
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| FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1));
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POKE32(PANEL_VERTICAL_TOTAL,
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FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1)
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| FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1));
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POKE32(PANEL_VERTICAL_SYNC,
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FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
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| FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
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ulTmpValue = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)|
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FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)|
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FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity)|
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FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE)|
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FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE);
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ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
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FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
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FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE)|
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FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW);
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ulReg = (PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits)
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& FIELD_CLEAR(PANEL_DISPLAY_CTRL, CLOCK_PHASE)
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& FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE)
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& FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE)
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& FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING)
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& FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE);
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/* May a hardware bug or just my test chip (not confirmed).
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* PANEL_DISPLAY_CTRL register seems requiring few writes
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* before a value can be successfully written in.
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* Added some masks to mask out the reserved bits.
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* Note: This problem happens by design. The hardware will wait for the
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* next vertical sync to turn on/off the plane.
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*/
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POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg);
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#if 1
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while((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg))
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{
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cnt++;
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if(cnt > 1000)
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break;
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POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg);
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}
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#endif
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}
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else{
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ret = -1;
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}
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return ret;
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}
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int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock)
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{
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pll_value_t pll;
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unsigned int uiActualPixelClk;
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pll.inputFreq = DEFAULT_INPUT_CLOCK;
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pll.clockType = clock;
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uiActualPixelClk = calcPllValue(parm->pixel_clock, &pll);
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if(getChipType() == SM750LE){
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/* set graphic mode via IO method */
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outb_p(0x88, 0x3d4);
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outb_p(0x06, 0x3d5);
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}
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programModeRegisters(parm, &pll);
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return 0;
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}
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