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![Christophe Leroy](/assets/img/avatar_default.png)
Flushing functions don't rely on preemption being disabled, so use kmap_local_page() instead of kmap_atomic(). Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/b6a880ea0ec7886b51edbb4979c188be549231c0.1617895813.git.christophe.leroy@csgroup.eu
234 lines
5.9 KiB
C
234 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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#include <linux/highmem.h>
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#include <linux/kprobes.h>
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/**
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* flush_coherent_icache() - if a CPU has a coherent icache, flush it
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* Return true if the cache was flushed, false otherwise
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*/
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static inline bool flush_coherent_icache(void)
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{
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/*
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* For a snooping icache, we still need a dummy icbi to purge all the
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* prefetched instructions from the ifetch buffers. We also need a sync
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* before the icbi to order the the actual stores to memory that might
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* have modified instructions with the icbi.
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*/
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if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
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mb(); /* sync */
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icbi((void *)PAGE_OFFSET);
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mb(); /* sync */
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isync();
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return true;
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}
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return false;
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}
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/**
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* invalidate_icache_range() - Flush the icache by issuing icbi across an address range
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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static void invalidate_icache_range(unsigned long start, unsigned long stop)
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{
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unsigned long shift = l1_icache_shift();
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unsigned long bytes = l1_icache_bytes();
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char *addr = (char *)(start & ~(bytes - 1));
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unsigned long size = stop - (unsigned long)addr + (bytes - 1);
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unsigned long i;
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for (i = 0; i < size >> shift; i++, addr += bytes)
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icbi(addr);
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mb(); /* sync */
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isync();
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}
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/**
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* flush_icache_range: Write any modified data cache blocks out to memory
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* and invalidate the corresponding blocks in the instruction cache
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*
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* Generic code will call this after writing memory, before executing from it.
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*
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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void flush_icache_range(unsigned long start, unsigned long stop)
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{
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if (flush_coherent_icache())
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return;
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clean_dcache_range(start, stop);
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if (IS_ENABLED(CONFIG_44x)) {
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/*
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* Flash invalidate on 44x because we are passed kmapped
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* addresses and this doesn't work for userspace pages due to
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* the virtually tagged icache.
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*/
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iccci((void *)start);
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mb(); /* sync */
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isync();
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} else
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invalidate_icache_range(start, stop);
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}
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EXPORT_SYMBOL(flush_icache_range);
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#ifdef CONFIG_HIGHMEM
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/**
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* flush_dcache_icache_phys() - Flush a page by it's physical address
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* @physaddr: the physical address of the page
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*/
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static void flush_dcache_icache_phys(unsigned long physaddr)
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{
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unsigned long bytes = l1_dcache_bytes();
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unsigned long nb = PAGE_SIZE / bytes;
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unsigned long addr = physaddr & PAGE_MASK;
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unsigned long msr, msr0;
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unsigned long loop1 = addr, loop2 = addr;
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msr0 = mfmsr();
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msr = msr0 & ~MSR_DR;
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/*
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* This must remain as ASM to prevent potential memory accesses
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* while the data MMU is disabled
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*/
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asm volatile(
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" mtctr %2;\n"
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" mtmsr %3;\n"
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" isync;\n"
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"0: dcbst 0, %0;\n"
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" addi %0, %0, %4;\n"
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" bdnz 0b;\n"
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" sync;\n"
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" mtctr %2;\n"
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"1: icbi 0, %1;\n"
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" addi %1, %1, %4;\n"
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" bdnz 1b;\n"
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" sync;\n"
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" mtmsr %5;\n"
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" isync;\n"
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: "+&r" (loop1), "+&r" (loop2)
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: "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
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: "ctr", "memory");
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}
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NOKPROBE_SYMBOL(flush_dcache_icache_phys)
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#else
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static void flush_dcache_icache_phys(unsigned long physaddr)
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{
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}
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#endif
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/**
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* __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* @p: the address of the page to flush
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*/
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static void __flush_dcache_icache(void *p)
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{
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unsigned long addr = (unsigned long)p & PAGE_MASK;
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clean_dcache_range(addr, addr + PAGE_SIZE);
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/*
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* We don't flush the icache on 44x. Those have a virtual icache and we
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* don't have access to the virtual address here (it's not the page
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* vaddr but where it's mapped in user space). The flushing of the
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* icache on these is handled elsewhere, when a change in the address
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* space occurs, before returning to user space.
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*/
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if (mmu_has_feature(MMU_FTR_TYPE_44x))
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return;
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invalidate_icache_range(addr, addr + PAGE_SIZE);
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}
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static void flush_dcache_icache_hugepage(struct page *page)
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{
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int i;
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int nr = compound_nr(page);
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if (!PageHighMem(page)) {
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for (i = 0; i < nr; i++)
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__flush_dcache_icache(lowmem_page_address(page + i));
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} else {
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for (i = 0; i < nr; i++) {
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void *start = kmap_local_page(page + i);
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__flush_dcache_icache(start);
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kunmap_local(start);
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}
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}
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}
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void flush_dcache_icache_page(struct page *page)
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{
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if (flush_coherent_icache())
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return;
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if (PageCompound(page))
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return flush_dcache_icache_hugepage(page);
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if (!PageHighMem(page)) {
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__flush_dcache_icache(lowmem_page_address(page));
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} else if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
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void *start = kmap_local_page(page);
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__flush_dcache_icache(start);
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kunmap_local(start);
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} else {
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flush_dcache_icache_phys(page_to_phys(page));
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}
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}
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EXPORT_SYMBOL(flush_dcache_icache_page);
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void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
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{
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clear_page(page);
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/*
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* We shouldn't have to do this, but some versions of glibc
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* require it (ld.so assumes zero filled pages are icache clean)
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* - Anton
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*/
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flush_dcache_page(pg);
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}
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EXPORT_SYMBOL(clear_user_page);
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void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
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struct page *pg)
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{
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copy_page(vto, vfrom);
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/*
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* We should be able to use the following optimisation, however
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* there are two problems.
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* Firstly a bug in some versions of binutils meant PLT sections
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* were not marked executable.
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* Secondly the first word in the GOT section is blrl, used
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* to establish the GOT address. Until recently the GOT was
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* not marked executable.
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* - Anton
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*/
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#if 0
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if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
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return;
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#endif
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flush_dcache_page(pg);
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}
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void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len)
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{
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void *maddr;
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maddr = kmap_local_page(page) + (addr & ~PAGE_MASK);
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flush_icache_range((unsigned long)maddr, (unsigned long)maddr + len);
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kunmap_local(maddr);
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}
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