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c45361abb9
When CONFIG_SMP=y, timebase synchronization is required when the second
kernel is started.
arch/powerpc/kernel/smp.c:
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
...
if (smp_ops->give_timebase)
smp_ops->give_timebase();
...
}
void start_secondary(void *unused)
{
...
if (smp_ops->take_timebase)
smp_ops->take_timebase();
...
}
When CONFIG_HOTPLUG_CPU=n and CONFIG_KEXEC_CORE=n,
smp_85xx_ops.give_timebase is NULL,
smp_85xx_ops.take_timebase is NULL,
As a result, the timebase is not synchronized.
Timebase synchronization does not depend on CONFIG_HOTPLUG_CPU.
Fixes: 56f1ba2807 ("powerpc/mpc85xx: refactor the PM operations")
Cc: stable@vger.kernel.org # v4.6+
Signed-off-by: Xiaoming Ni <nixiaoming@huawei.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210929033646.39630-3-nixiaoming@huawei.com
105 lines
1.9 KiB
C
105 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC85xx PM operators
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*
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* Copyright 2015 Freescale Semiconductor Inc.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/fsl/guts.h>
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#include <asm/io.h>
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#include <asm/fsl_pm.h>
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static struct ccsr_guts __iomem *guts;
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#ifdef CONFIG_FSL_PMC
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static void mpc85xx_irq_mask(int cpu)
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{
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}
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static void mpc85xx_irq_unmask(int cpu)
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{
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}
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static void mpc85xx_cpu_die(int cpu)
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{
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u32 tmp;
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tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
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mtspr(SPRN_HID0, tmp);
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/* Enter NAP mode. */
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tmp = mfmsr();
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tmp |= MSR_WE;
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asm volatile(
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"msync\n"
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"mtmsr %0\n"
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"isync\n"
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:
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: "r" (tmp));
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}
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static void mpc85xx_cpu_up_prepare(int cpu)
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{
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}
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#endif
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static void mpc85xx_freeze_time_base(bool freeze)
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{
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uint32_t mask;
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mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
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if (freeze)
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setbits32(&guts->devdisr, mask);
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else
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clrbits32(&guts->devdisr, mask);
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in_be32(&guts->devdisr);
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}
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static const struct of_device_id mpc85xx_smp_guts_ids[] = {
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{ .compatible = "fsl,mpc8572-guts", },
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{ .compatible = "fsl,p1020-guts", },
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{ .compatible = "fsl,p1021-guts", },
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{ .compatible = "fsl,p1022-guts", },
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{ .compatible = "fsl,p1023-guts", },
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{ .compatible = "fsl,p2020-guts", },
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{ .compatible = "fsl,bsc9132-guts", },
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{},
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};
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static const struct fsl_pm_ops mpc85xx_pm_ops = {
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.freeze_time_base = mpc85xx_freeze_time_base,
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#ifdef CONFIG_FSL_PMC
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.irq_mask = mpc85xx_irq_mask,
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.irq_unmask = mpc85xx_irq_unmask,
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.cpu_die = mpc85xx_cpu_die,
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.cpu_up_prepare = mpc85xx_cpu_up_prepare,
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#endif
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};
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int __init mpc85xx_setup_pmc(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
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if (np) {
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guts = of_iomap(np, 0);
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of_node_put(np);
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if (!guts) {
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pr_err("Could not map guts node address\n");
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return -ENOMEM;
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}
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qoriq_pm_ops = &mpc85xx_pm_ops;
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}
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return 0;
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}
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