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6c0afb5039
Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
141 lines
4 KiB
C
141 lines
4 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.c
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/of_address.h>
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#include <asm/cpu.h>
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#include <trace/events/power.h>
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#include "soc.h"
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#include "clockdomain.h"
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#include "clock.h"
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#include "cm.h"
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#include "cm2xxx.h"
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#include "cm3xxx.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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#include "common.h"
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u16 cpu_mask;
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/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
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#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
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#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
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#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
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/*
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* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
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* From device data manual section 4.3 "DPLL and DLL Specifications".
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*/
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#define OMAP3PLUS_DPLL_FINT_MIN 32000
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#define OMAP3PLUS_DPLL_FINT_MAX 52000000
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struct ti_clk_ll_ops omap_clk_ll_ops = {
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.clkdm_clk_enable = clkdm_clk_enable,
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.clkdm_clk_disable = clkdm_clk_disable,
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.clkdm_lookup = clkdm_lookup,
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.cm_wait_module_ready = omap_cm_wait_module_ready,
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.cm_split_idlest_reg = cm_split_idlest_reg,
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};
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/**
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* omap2_clk_setup_ll_ops - setup clock driver low-level ops
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*
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* Sets up clock driver low-level platform ops. These are needed
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* for register accesses and various other misc platform operations.
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* Returns 0 on success, -EBUSY if low level ops have been registered
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* already.
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*/
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int __init omap2_clk_setup_ll_ops(void)
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{
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return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
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}
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/*
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* OMAP2+ specific clock functions
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*/
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/**
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* ti_clk_init_features - init clock features struct for the SoC
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*
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* Initializes the clock features struct based on the SoC type.
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*/
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void __init ti_clk_init_features(void)
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{
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struct ti_clk_features features = { 0 };
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/* Fint setup for DPLLs */
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if (cpu_is_omap3430()) {
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features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
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features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
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features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
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features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
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} else {
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features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
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features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
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}
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/* Bypass value setup for DPLLs */
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if (cpu_is_omap24xx()) {
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features.dpll_bypass_vals |=
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(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
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(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
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} else if (cpu_is_omap34xx()) {
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features.dpll_bypass_vals |=
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(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
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(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
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} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
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soc_is_omap54xx() || soc_is_dra7xx()) {
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features.dpll_bypass_vals |=
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(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
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(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
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(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
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}
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/* Jitter correction only available on OMAP343X */
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if (cpu_is_omap343x())
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features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
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/* Idlest value for interface clocks.
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* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
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* 34xx reverses this, just to keep us on our toes
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* AM35xx uses both, depending on the module.
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*/
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if (cpu_is_omap24xx())
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features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
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else if (cpu_is_omap34xx())
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features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
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/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
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if (omap_rev() == OMAP3430_REV_ES1_0)
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features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
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/* Errata I810 for omap5 / dra7 */
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if (soc_is_omap54xx() || soc_is_dra7xx())
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features.flags |= TI_CLK_ERRATA_I810;
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ti_clk_setup_features(&features);
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}
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