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![Arnd Bergmann](/assets/img/avatar_default.png)
Second set of OMAP PRCM cleanups for 3.8. These patches remove the use of omap_prcm_get_reset_sources() from the OMAP watchdog driver, and remove mach-omap2/prcm.c and plat-omap/include/plat/prcm.h. Basic test logs for this branch on top of Tony's cleanup-prcm branch at commit7fc54fd308
are here: http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121108151646/ However, cleanup-prcm at7fc54fd3
does not include some fixes that are needed for a successful test. With several reverts, fixes, and workarounds applied, the following test logs were obtained: http://www.pwsan.com/omap/testlogs/TEST_prcm_cleanup_b_3.8/20121108151930/ which indicate that the series tests cleanly. This second pull request updates one of the patches which broke with rmk's allnoconfigs, and also updates the tag description to indicate that7fc54fd3
is building cleanly here. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQoY0GAAoJEBvUPslcq6Vza0MQAI0idVoOclIHCC63tpc58YWA BpD5OLg4yRu0RUFS1CI/Fq5d+9PfYUspgaWja3TTgUy0EHRDVUUFRaxJdpWdl2NF gX7BCuhnQenznTbCE80nEmxvsh7U/dfvs+JYUK2PriypU61f1+TnSu9ZxTRvDJOx vbo1cfsioVcLfnBPSDSQVJ1fufbafklpeQkDNeRI8UDsCVeXwnxhNsXB3utoJMf0 5gaDaCdRBoimkLnAaLi41OnHYC7IbNCnl/VX0i/xffROsINfL7LDkBPfUOnR5vle jTCV49UEB/P5ekk2cvKKj8IOQZdimiCppWMLit6DObX7LbltTKuXx6T0PclgxQ14 hhav5O+f8NYA4yDAY/xxPlTvShMr8rQcYV6pg1G1OgD+dcq7cbbWNJAvbUJ03hH8 dqZ+ypLYkazb3Mm5XtpFr47gkoaFnCQbgZLXpjJ8+L01aGNrF2L6aE789So1N81+ X1s0ENjRxzDLNcqwxqhcoph0YQe7GlyiviYb7ev25MTSC3/TjrupTViZbKocZmLt Ad9m4SOktbHthAw0jdA48vOmPiSvmYzFiqzMhz/ryeNbyyV6rRxe5w4JUjPzHPxc U7NraSGIAzpqM3EKEp7Rb0yOfh6sGzML/FH9bS25+Rv37yKW0huc6ENIRgatZpY2 blLzsxaKfQgLeqKT82mj =tS2z -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.8/cleanup-prcm-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup From Tony Lindgren <tony@atomide.com>: More PRCM cleanups via Paul Walmsley <paul@pwsan.com>: Second set of OMAP PRCM cleanups for 3.8. These patches remove the use of omap_prcm_get_reset_sources() from the OMAP watchdog driver, and remove mach-omap2/prcm.c and plat-omap/include/plat/prcm.h. Basic test logs for this branch on top of Tony's cleanup-prcm branch at commit7fc54fd308
are here: http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121108151646/ However, cleanup-prcm at7fc54fd3
does not include some fixes that are needed for a successful test. With several reverts, fixes, and workarounds applied, the following test logs were obtained: http://www.pwsan.com/omap/testlogs/TEST_prcm_cleanup_b_3.8/20121108151930/ which indicate that the series tests cleanly. This second pull request updates one of the patches which broke with rmk's allnoconfigs, and also updates the tag description to indicate that7fc54fd3
is building cleanly here. * tag 'omap-for-v3.8/cleanup-prcm-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (27 commits) ARM: OMAP2: Fix compillation error in cm_common ARM: OMAP2+: PRCM: remove obsolete prcm.[ch] ARM: OMAP2+: hwmod: call to _omap4_disable_module() should use the SoC-specific call ARM: OMAP2+: PRCM: consolidate PRCM-related timeout macros ARM: OMAP2+: PRCM: split and relocate the PRM/CM globals setup ARM: OMAP2+: PRCM: remove omap2_cm_wait_idlest() ARM: OMAP2+: CM/clock: convert _omap2_module_wait_ready() to use SoC-independent CM functions ARM: OMAP2xxx: APLL/CM: convert to use omap2_cm_wait_module_ready() ARM: OMAP2+: board files: use SoC-specific system restart functions ARM: OMAP2+: PRCM: create SoC-specific chip restart functions ARM: OMAP2xxx: clock: move virt_prcm_set code into clkt2xxx_virt_prcm_set.c ARM: OMAP2xxx: clock: remove global 'dclk' variable ARM: OMAP2/3: PRM: add SoC reset functions (using the CORE DPLL method) ARM: OMAP2+: common: remove mach-omap2/common.c globals and map_common_io code ARM: OMAP2+: PRCM: remove omap_prcm_get_reset_sources() watchdog: OMAP: use standard GETBOOTSTATUS interface; use platform_data fn ptr ARM: OMAP2+: WDT: move init; add read_reset_sources pdata function pointer ARM: OMAP1: CGRM: fix omap1_get_reset_sources() return type ARM: OMAP2+: PRM: create PRM reset source API for the watchdog timer driver ARM: OMAP1: create read_reset_sources() function (for initial use by watchdog) ... Conflicts: arch/arm/mach-omap2/cm33xx.c arch/arm/mach-omap2/io.c arch/arm/mach-omap2/prm_common.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
157 lines
4 KiB
C
157 lines
4 KiB
C
/*
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* SMS/SDRC (SDRAM controller) common code for OMAP2/3
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*
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* Copyright (C) 2005, 2008 Texas Instruments Inc.
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* Copyright (C) 2005, 2008 Nokia Corporation
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*
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* Tony Lindgren <tony@atomide.com>
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* Paul Walmsley
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "common.h"
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#include "clock.h"
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#include "sdrc.h"
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static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
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void __iomem *omap2_sdrc_base;
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void __iomem *omap2_sms_base;
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struct omap2_sms_regs {
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u32 sms_sysconfig;
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};
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static struct omap2_sms_regs sms_context;
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/* SDRC_POWER register bits */
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#define SDRC_POWER_EXTCLKDIS_SHIFT 3
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#define SDRC_POWER_PWDENA_SHIFT 2
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#define SDRC_POWER_PAGEPOLICY_SHIFT 0
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/**
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* omap2_sms_save_context - Save SMS registers
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*
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* Save SMS registers that need to be restored after off mode.
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*/
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void omap2_sms_save_context(void)
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{
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sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
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}
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/**
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* omap2_sms_restore_context - Restore SMS registers
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*
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* Restore SMS registers that need to be Restored after off mode.
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*/
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void omap2_sms_restore_context(void)
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{
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sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
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}
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/**
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* omap2_sdrc_get_params - return SDRC register values for a given clock rate
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* @r: SDRC clock rate (in Hz)
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* @sdrc_cs0: chip select 0 ram timings **
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* @sdrc_cs1: chip select 1 ram timings **
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*
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* Return pre-calculated values for the SDRC_ACTIM_CTRLA,
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* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
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* structs,for a given SDRC clock rate 'r'.
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* These parameters control various timing delays in the SDRAM controller
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* that are expressed in terms of the number of SDRC clock cycles to
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* wait; hence the clock rate dependency.
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*
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* Supports 2 different timing parameters for both chip selects.
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*
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* Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
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* Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
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* as sdrc_init_params_cs_0.
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*
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* Fills in the struct omap_sdrc_params * for each chip select.
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* Returns 0 upon success or -1 upon failure.
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*/
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int omap2_sdrc_get_params(unsigned long r,
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struct omap_sdrc_params **sdrc_cs0,
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struct omap_sdrc_params **sdrc_cs1)
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{
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struct omap_sdrc_params *sp0, *sp1;
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if (!sdrc_init_params_cs0)
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return -1;
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sp0 = sdrc_init_params_cs0;
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sp1 = sdrc_init_params_cs1;
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while (sp0->rate && sp0->rate != r) {
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sp0++;
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if (sdrc_init_params_cs1)
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sp1++;
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}
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if (!sp0->rate)
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return -1;
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*sdrc_cs0 = sp0;
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*sdrc_cs1 = sp1;
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return 0;
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}
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void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
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{
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omap2_sdrc_base = sdrc;
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omap2_sms_base = sms;
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}
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/**
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* omap2_sdrc_init - initialize SMS, SDRC devices on boot
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* @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
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* Support for 2 chip selects timings
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*
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* Turn on smart idle modes for SDRAM scheduler and controller.
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* Program a known-good configuration for the SDRC to deal with buggy
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* bootloaders.
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*/
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void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
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struct omap_sdrc_params *sdrc_cs1)
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{
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u32 l;
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l = sms_read_reg(SMS_SYSCONFIG);
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l &= ~(0x3 << 3);
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l |= (0x2 << 3);
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sms_write_reg(l, SMS_SYSCONFIG);
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l = sdrc_read_reg(SDRC_SYSCONFIG);
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l &= ~(0x3 << 3);
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l |= (0x2 << 3);
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sdrc_write_reg(l, SDRC_SYSCONFIG);
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sdrc_init_params_cs0 = sdrc_cs0;
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sdrc_init_params_cs1 = sdrc_cs1;
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/* XXX Enable SRFRONIDLEREQ here also? */
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/*
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* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
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* can cause random memory corruption
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*/
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l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
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(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
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sdrc_write_reg(l, SDRC_POWER);
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omap2_sms_save_context();
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}
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