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b0402717c9
The IDE bit in the CONFF register is the third bit not the fourth. Signed-off-by: Thomas Niederprüm <niederp@physik.uni-kl.de> Signed-off-by: Mark Brown <broonie@kernel.org>
211 lines
5.7 KiB
C
211 lines
5.7 KiB
C
/*
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* Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
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*
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* Copyright: 2011 Raumfeld GmbH
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* Author: Johannes Stezenbach <js@sig21.net>
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*
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* based on code from:
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* Wolfson Microelectronics PLC.
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* Mark Brown <broonie@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASOC_STA_32X_H
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#define _ASOC_STA_32X_H
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/* STA326 register addresses */
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#define STA32X_REGISTER_COUNT 0x2d
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#define STA32X_COEF_COUNT 62
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#define STA32X_CONFA 0x00
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#define STA32X_CONFB 0x01
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#define STA32X_CONFC 0x02
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#define STA32X_CONFD 0x03
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#define STA32X_CONFE 0x04
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#define STA32X_CONFF 0x05
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#define STA32X_MMUTE 0x06
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#define STA32X_MVOL 0x07
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#define STA32X_C1VOL 0x08
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#define STA32X_C2VOL 0x09
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#define STA32X_C3VOL 0x0a
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#define STA32X_AUTO1 0x0b
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#define STA32X_AUTO2 0x0c
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#define STA32X_AUTO3 0x0d
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#define STA32X_C1CFG 0x0e
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#define STA32X_C2CFG 0x0f
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#define STA32X_C3CFG 0x10
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#define STA32X_TONE 0x11
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#define STA32X_L1AR 0x12
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#define STA32X_L1ATRT 0x13
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#define STA32X_L2AR 0x14
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#define STA32X_L2ATRT 0x15
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#define STA32X_CFADDR2 0x16
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#define STA32X_B1CF1 0x17
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#define STA32X_B1CF2 0x18
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#define STA32X_B1CF3 0x19
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#define STA32X_B2CF1 0x1a
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#define STA32X_B2CF2 0x1b
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#define STA32X_B2CF3 0x1c
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#define STA32X_A1CF1 0x1d
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#define STA32X_A1CF2 0x1e
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#define STA32X_A1CF3 0x1f
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#define STA32X_A2CF1 0x20
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#define STA32X_A2CF2 0x21
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#define STA32X_A2CF3 0x22
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#define STA32X_B0CF1 0x23
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#define STA32X_B0CF2 0x24
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#define STA32X_B0CF3 0x25
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#define STA32X_CFUD 0x26
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#define STA32X_MPCC1 0x27
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#define STA32X_MPCC2 0x28
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/* Reserved 0x29 */
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/* Reserved 0x2a */
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#define STA32X_Reserved 0x2a
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#define STA32X_FDRC1 0x2b
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#define STA32X_FDRC2 0x2c
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/* Reserved 0x2d */
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/* STA326 register field definitions */
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/* 0x00 CONFA */
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#define STA32X_CONFA_MCS_MASK 0x03
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#define STA32X_CONFA_MCS_SHIFT 0
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#define STA32X_CONFA_IR_MASK 0x18
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#define STA32X_CONFA_IR_SHIFT 3
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#define STA32X_CONFA_TWRB 0x20
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#define STA32X_CONFA_TWAB 0x40
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#define STA32X_CONFA_FDRB 0x80
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/* 0x01 CONFB */
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#define STA32X_CONFB_SAI_MASK 0x0f
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#define STA32X_CONFB_SAI_SHIFT 0
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#define STA32X_CONFB_SAIFB 0x10
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#define STA32X_CONFB_DSCKE 0x20
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#define STA32X_CONFB_C1IM 0x40
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#define STA32X_CONFB_C2IM 0x80
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/* 0x02 CONFC */
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#define STA32X_CONFC_OM_MASK 0x03
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#define STA32X_CONFC_OM_SHIFT 0
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#define STA32X_CONFC_CSZ_MASK 0x7c
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#define STA32X_CONFC_CSZ_SHIFT 2
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/* 0x03 CONFD */
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#define STA32X_CONFD_HPB 0x01
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#define STA32X_CONFD_HPB_SHIFT 0
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#define STA32X_CONFD_DEMP 0x02
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#define STA32X_CONFD_DEMP_SHIFT 1
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#define STA32X_CONFD_DSPB 0x04
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#define STA32X_CONFD_DSPB_SHIFT 2
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#define STA32X_CONFD_PSL 0x08
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#define STA32X_CONFD_PSL_SHIFT 3
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#define STA32X_CONFD_BQL 0x10
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#define STA32X_CONFD_BQL_SHIFT 4
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#define STA32X_CONFD_DRC 0x20
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#define STA32X_CONFD_DRC_SHIFT 5
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#define STA32X_CONFD_ZDE 0x40
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#define STA32X_CONFD_ZDE_SHIFT 6
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#define STA32X_CONFD_MME 0x80
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#define STA32X_CONFD_MME_SHIFT 7
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/* 0x04 CONFE */
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#define STA32X_CONFE_MPCV 0x01
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#define STA32X_CONFE_MPCV_SHIFT 0
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#define STA32X_CONFE_MPC 0x02
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#define STA32X_CONFE_MPC_SHIFT 1
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#define STA32X_CONFE_AME 0x08
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#define STA32X_CONFE_AME_SHIFT 3
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#define STA32X_CONFE_PWMS 0x10
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#define STA32X_CONFE_PWMS_SHIFT 4
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#define STA32X_CONFE_ZCE 0x40
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#define STA32X_CONFE_ZCE_SHIFT 6
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#define STA32X_CONFE_SVE 0x80
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#define STA32X_CONFE_SVE_SHIFT 7
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/* 0x05 CONFF */
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#define STA32X_CONFF_OCFG_MASK 0x03
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#define STA32X_CONFF_OCFG_SHIFT 0
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#define STA32X_CONFF_IDE 0x04
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#define STA32X_CONFF_IDE_SHIFT 2
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#define STA32X_CONFF_BCLE 0x08
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#define STA32X_CONFF_ECLE 0x20
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#define STA32X_CONFF_PWDN 0x40
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#define STA32X_CONFF_EAPD 0x80
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/* 0x06 MMUTE */
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#define STA32X_MMUTE_MMUTE 0x01
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/* 0x0b AUTO1 */
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#define STA32X_AUTO1_AMEQ_MASK 0x03
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#define STA32X_AUTO1_AMEQ_SHIFT 0
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#define STA32X_AUTO1_AMV_MASK 0xc0
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#define STA32X_AUTO1_AMV_SHIFT 2
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#define STA32X_AUTO1_AMGC_MASK 0x30
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#define STA32X_AUTO1_AMGC_SHIFT 4
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#define STA32X_AUTO1_AMPS 0x80
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/* 0x0c AUTO2 */
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#define STA32X_AUTO2_AMAME 0x01
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#define STA32X_AUTO2_AMAM_MASK 0x0e
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#define STA32X_AUTO2_AMAM_SHIFT 1
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#define STA32X_AUTO2_XO_MASK 0xf0
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#define STA32X_AUTO2_XO_SHIFT 4
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/* 0x0d AUTO3 */
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#define STA32X_AUTO3_PEQ_MASK 0x1f
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#define STA32X_AUTO3_PEQ_SHIFT 0
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/* 0x0e 0x0f 0x10 CxCFG */
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#define STA32X_CxCFG_TCB 0x01 /* only C1 and C2 */
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#define STA32X_CxCFG_TCB_SHIFT 0
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#define STA32X_CxCFG_EQBP 0x02 /* only C1 and C2 */
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#define STA32X_CxCFG_EQBP_SHIFT 1
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#define STA32X_CxCFG_VBP 0x03
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#define STA32X_CxCFG_VBP_SHIFT 2
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#define STA32X_CxCFG_BO 0x04
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#define STA32X_CxCFG_LS_MASK 0x30
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#define STA32X_CxCFG_LS_SHIFT 4
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#define STA32X_CxCFG_OM_MASK 0xc0
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#define STA32X_CxCFG_OM_SHIFT 6
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/* 0x11 TONE */
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#define STA32X_TONE_BTC_SHIFT 0
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#define STA32X_TONE_TTC_SHIFT 4
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/* 0x12 0x13 0x14 0x15 limiter attack/release */
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#define STA32X_LxA_SHIFT 0
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#define STA32X_LxR_SHIFT 4
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/* 0x26 CFUD */
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#define STA32X_CFUD_W1 0x01
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#define STA32X_CFUD_WA 0x02
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#define STA32X_CFUD_R1 0x04
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#define STA32X_CFUD_RA 0x08
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/* biquad filter coefficient table offsets */
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#define STA32X_C1_BQ_BASE 0
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#define STA32X_C2_BQ_BASE 20
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#define STA32X_CH_BQ_NUM 4
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#define STA32X_BQ_NUM_COEF 5
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#define STA32X_XO_HP_BQ_BASE 40
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#define STA32X_XO_LP_BQ_BASE 45
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#define STA32X_C1_PRESCALE 50
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#define STA32X_C2_PRESCALE 51
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#define STA32X_C1_POSTSCALE 52
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#define STA32X_C2_POSTSCALE 53
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#define STA32X_C3_POSTSCALE 54
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#define STA32X_TW_POSTSCALE 55
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#define STA32X_C1_MIX1 56
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#define STA32X_C1_MIX2 57
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#define STA32X_C2_MIX1 58
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#define STA32X_C2_MIX2 59
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#define STA32X_C3_MIX1 60
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#define STA32X_C3_MIX2 61
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#endif /* _ASOC_STA_32X_H */
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