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e16415313c
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
104 lines
1.9 KiB
Text
104 lines
1.9 KiB
Text
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx6q.dtsi"
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/ {
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model = "Freescale i.MX6 Quad Armadillo2 Board";
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compatible = "fsl,imx6q-arm2", "fsl,imx6q";
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memory {
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reg = <0x10000000 0x80000000>;
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};
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regulators {
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compatible = "simple-bus";
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reg_3p3v: 3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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leds {
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compatible = "gpio-leds";
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debug-led {
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label = "Heartbeat";
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gpios = <&gpio3 25 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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status = "disabled"; /* gpmi nand conflicts with SD */
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
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>;
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};
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};
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arm2 {
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pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
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fsl,pins = <
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MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
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MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
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>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet_2>;
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phy-mode = "rgmii";
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status = "okay";
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};
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&usdhc3 {
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cd-gpios = <&gpio6 11 0>;
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wp-gpios = <&gpio6 14 0>;
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vmmc-supply = <®_3p3v>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3_1
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&pinctrl_usdhc3_arm2>;
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status = "okay";
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};
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&usdhc4 {
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non-removable;
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vmmc-supply = <®_3p3v>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4_1>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4_1>;
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status = "okay";
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};
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