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StarFive: Things are a bit slower for StarFive this window, there's only the addition of audio related DT nodes to speak of here. Generic: The SiFive, StarFive and Microchip devicetrees have had my replacement ISA extension detection properties added. Unfortunately, the old "riscv,isa" property never defined exactly what the extensions it contained meant, and people were want to fill it in incorrectly (and call upstream kernel devs idiots for not doing the same). The new properties have explicit definitions and hopefully will stand up better to some of the variation from RVI. Sophgo: Two new SoCs, one is probably the first of several with up/down tuned variants, that have a pair of T-Head c906 cores and appear aimed at the IP camera, smart <insert whatever> etc markets. They are intended to run in AMP mode, with an RTOS on the less powerful core. The other is far more interesting to kernel developers however, the 64-core SG2042, with more recent c920 cores from T-Head at 2 GHz. For both, support is at a very basic stage - some of the same developers are working on them as other T-Head powered SoCs, but hopefully things will move beyond a basic console boot. The goal is for Chen Wang to take over maintaining the Sophgo support once they have some more experience with the process. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZS1W8gAKCRB4tDGHoIJi 0mLBAP9fhiekHB8O7VQpcGvPB3FgFFh7uP8DzKcpU6bW8PbNmgD+MoCp4d/amMFR VCtONbvM+RYC1ENRaOY91gI3k/2b0w8= =2vZu -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmUv5cgACgkQYKtH/8kJ Uie+/hAA1WrNmS794Ab3VKazNPGXtH2ZtvZ875l7H4Zn/6lFsw21UyB3CBl70yVM qK4OxG5TTHMCbhi0YvW2zJs8jtW7ogYTVFm68q0KiJH3kWWrpAFrzGhtmz1jDTwv FnKxVQCNMcoTgDqwIQ2pgoirP9yxxdk4EBnqWYgwWRLgHLJtr0MMoQiwJCbTXhTB ajzzjvWWkv3pG0VZY4gDm2l1kIqd5FSEClr9a8dG2dFg4kR3omkKJ1o3kk3Fs+/E vcYel6ge+V/RJ503e3OH0YopHJIicYqGB+04cxdhyHdB7NRz9URaplOF+MP1eadY iRnz9wkTHeJqFIBwYAV8vKhqrjQlEIvfP4+2QTupGvmGiw5xrtAy7ow5D+hTiLQ4 EGNVGHrpXV3YTzS6PyNJVco3c5yFKABXBkMBvxy0/f3QdwF8a+LFzm05TOm9dosA bzvrN6I0qdCpUFqaho3j30RmL4o2rjF85z6hSZnNU6h9qw3Jdu3QaL44R3KbfeU2 ivxhFk4jbEdigk3lq/NTUHK8PIgAN3nRpuSWCk2HojLMEvU0EsyNBjihc/50WhoL D7qno7G2L2xhKRkpSu9ClPEODcrexhcqBzHoRPUuN53jpqN3Wrva/pRtjfm25EID GOcypde5vfVHR2krKnH7zXLwmk7bkxgcsTIoVauH/u+DdO+E/8o= =76M7 -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.7 StarFive: Things are a bit slower for StarFive this window, there's only the addition of audio related DT nodes to speak of here. Generic: The SiFive, StarFive and Microchip devicetrees have had my replacement ISA extension detection properties added. Unfortunately, the old "riscv,isa" property never defined exactly what the extensions it contained meant, and people were want to fill it in incorrectly (and call upstream kernel devs idiots for not doing the same). The new properties have explicit definitions and hopefully will stand up better to some of the variation from RVI. Sophgo: Two new SoCs, one is probably the first of several with up/down tuned variants, that have a pair of T-Head c906 cores and appear aimed at the IP camera, smart <insert whatever> etc markets. They are intended to run in AMP mode, with an RTOS on the less powerful core. The other is far more interesting to kernel developers however, the 64-core SG2042, with more recent c920 cores from T-Head at 2 GHz. For both, support is at a very basic stage - some of the same developers are working on them as other T-Head powered SoCs, but hopefully things will move beyond a basic console boot. The goal is for Chen Wang to take over maintaining the Sophgo support once they have some more experience with the process. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (22 commits) riscv: dts: starfive: convert isa detection to new properties riscv: dts: sifive: convert isa detection to new properties riscv: dts: microchip: convert isa detection to new properties riscv: dts: sophgo: add Milk-V Duo board device tree riscv: dts: sophgo: add initial CV1800B SoC device tree dt-bindings: riscv: Add Milk-V Duo board compatibles dt-bindings: timer: Add SOPHGO CV1800B clint dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic riscv: defconfig: enable SOPHGO SoC riscv: dts: sophgo: add Milk-V Pioneer board device tree riscv: dts: add initial Sophgo SG2042 SoC device tree dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi dt-bindings: timer: Add Sophgo sg2042 CLINT timer dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC dt-bindings: riscv: Add T-HEAD C920 compatibles dt-bindings: riscv: add sophgo sg2042 bindings dt-bindings: vendor-prefixes: add milkv/sophgo riscv: Add SOPHGO SOC family Kconfig support riscv: dts: starfive: add assigned-clock* to limit frquency riscv: dts: starfive: Add JH7110 PWM-DAC support ... Link: https://lore.kernel.org/r/20231016-filing-payroll-7aca51b8f1a3@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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