Vineet Gupta 795f455856 ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency) ... L2 cache on ARCHS processors is called SLC (System Level Cache) For working DMA (in absence of hardware assisted IO Coherency) we need to manage SLC explicitly when buffers transition between cpu and controllers. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-06-25 06:00:19 +05:30
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cache.c	ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)	2015-06-25 06:00:19 +05:30
dma.c	ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)	2015-06-25 06:00:19 +05:30
extable.c	ARC: Fix coding style issues	2013-04-09 12:21:14 +05:30
fault.c	ARC: perf: Enable generic software events	2015-02-27 10:15:01 +05:30
init.c	ARC: mem init spring cleaning - No functional changes	2015-04-13 15:16:29 +05:30
ioremap.c	ARC: Use <linux/*> headers instead of <asm/*>	2013-04-09 12:21:14 +05:30
Makefile	ARC: mm/cache_arc700.c -> mm/cache.c	2015-06-19 18:09:32 +05:30
mmap.c	ARC: [mm] Aliasing VIPT dcache support 4/4	2013-05-09 22:00:57 +05:30
tlb.c	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30
tlbex.S	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30