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Part of the device initialization aligns the rising edge of the output clock to the internal 1 PPS clock. If the system APLL and DPLL is not locked, then the alignment will fail and there will be a fixed offset between the internal 1 PPS clock and the output clock. After loading the device firmware, poll the system APLL and DPLL for locked state prior to initialization, timing out after 2 seconds. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| idt8a340_reg.h | ||
| Kconfig | ||
| Makefile | ||
| ptp_chardev.c | ||
| ptp_clock.c | ||
| ptp_clockmatrix.c | ||
| ptp_clockmatrix.h | ||
| ptp_dte.c | ||
| ptp_idt82p33.c | ||
| ptp_idt82p33.h | ||
| ptp_ines.c | ||
| ptp_kvm.c | ||
| ptp_ocp.c | ||
| ptp_pch.c | ||
| ptp_private.h | ||
| ptp_qoriq.c | ||
| ptp_qoriq_debugfs.c | ||
| ptp_sysfs.c | ||
| ptp_vmw.c | ||