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42f51fb24f
... to avoid unwanted gcc optimizations SMP kernels fail to boot with commit596ff4a09b("cpumask: re-introduce constant-sized cpumask optimizations"). | | percpu: BUG: failure at mm/percpu.c:2981/pcpu_build_alloc_info()! | The write operation performed by the SCOND instruction in the atomic inline asm code is not properly passed to the compiler. The compiler cannot correctly optimize a nested loop that runs through the cpumask in the pcpu_build_alloc_info() function. Fix this by add a compiler barrier (memory clobber in inline asm). Apparently atomic ops used to have memory clobber implicitly via surrounding smp_mb(). However commitb64be68369("ARC: atomics: implement relaxed variants") removed the smp_mb() for the relaxed variants, but failed to add the explicit compiler barrier. Link: https://github.com/foss-for-synopsys-dwc-arc-processors/linux/issues/135 Cc: <stable@vger.kernel.org> # v6.3+ Fixes:b64be68369("ARC: atomics: implement relaxed variants") Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@kernel.org> [vgupta: tweaked the changelog and added Fixes tag]
97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_ARC_ATOMIC_LLSC_H
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#define _ASM_ARC_ATOMIC_LLSC_H
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#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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#define ATOMIC_OP(op, asm_op) \
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static inline void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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\
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__asm__ __volatile__( \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
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: [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
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[i] "ir" (i) \
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: "cc", "memory"); \
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} \
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#define ATOMIC_OP_RETURN(op, asm_op) \
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static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
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{ \
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unsigned int val; \
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\
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__asm__ __volatile__( \
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"1: llock %[val], [%[ctr]] \n" \
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" " #asm_op " %[val], %[val], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val) \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc", "memory"); \
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\
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return val; \
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}
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#define ATOMIC_FETCH_OP(op, asm_op) \
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static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
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{ \
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unsigned int val, orig; \
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\
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__asm__ __volatile__( \
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"1: llock %[orig], [%[ctr]] \n" \
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" " #asm_op " %[val], %[orig], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" bnz 1b \n" \
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: [val] "=&r" (val), \
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[orig] "=&r" (orig) \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc", "memory"); \
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\
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return orig; \
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}
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_andnot_relaxed arch_atomic_fetch_andnot_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_OP_RETURN(op, asm_op) \
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ATOMIC_FETCH_OP(op, asm_op)
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ATOMIC_OPS(add, add)
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ATOMIC_OPS(sub, sub)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_FETCH_OP(op, asm_op)
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ATOMIC_OPS(and, and)
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ATOMIC_OPS(andnot, bic)
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ATOMIC_OPS(or, or)
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ATOMIC_OPS(xor, xor)
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#define arch_atomic_andnot arch_atomic_andnot
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#endif
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