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4141f1a40f
In order to wake from suspend by ethernet magic packets the GPC
must be used as intc does not have wakeup functionality.
But the FEC DT node currently uses interrupt-extended,
specificying intc, thus breaking WoL.
This problem is probably fallout from the stacked domain conversion
as intc used to chain to GPC.
So replace "interrupts-extended" by "interrupts" to use the default
parent which is GPC.
Fixes: b923ff6af0 ("ARM: imx6: convert GPC to stacked domains")
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: David S. Miller <davem@davemloft.net>
114 lines
2.6 KiB
Text
114 lines
2.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Copyright 2016 Freescale Semiconductor, Inc.
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#include "imx6q.dtsi"
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/ {
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soc {
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ocram2: sram@940000 {
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compatible = "mmio-sram";
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reg = <0x00940000 0x20000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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ocram3: sram@960000 {
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compatible = "mmio-sram";
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reg = <0x00960000 0x20000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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bus@2100000 {
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pre1: pre@21c8000 {
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compatible = "fsl,imx6qp-pre";
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reg = <0x021c8000 0x1000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks IMX6QDL_CLK_PRE0>;
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clock-names = "axi";
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fsl,iram = <&ocram2>;
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};
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pre2: pre@21c9000 {
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compatible = "fsl,imx6qp-pre";
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reg = <0x021c9000 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks IMX6QDL_CLK_PRE1>;
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clock-names = "axi";
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fsl,iram = <&ocram2>;
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};
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pre3: pre@21ca000 {
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compatible = "fsl,imx6qp-pre";
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reg = <0x021ca000 0x1000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks IMX6QDL_CLK_PRE2>;
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clock-names = "axi";
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fsl,iram = <&ocram3>;
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};
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pre4: pre@21cb000 {
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compatible = "fsl,imx6qp-pre";
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reg = <0x021cb000 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks IMX6QDL_CLK_PRE3>;
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clock-names = "axi";
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fsl,iram = <&ocram3>;
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};
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prg1: prg@21cc000 {
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compatible = "fsl,imx6qp-prg";
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reg = <0x021cc000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
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<&clks IMX6QDL_CLK_PRG0_AXI>;
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clock-names = "ipg", "axi";
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fsl,pres = <&pre1>, <&pre2>, <&pre3>;
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};
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prg2: prg@21cd000 {
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compatible = "fsl,imx6qp-prg";
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reg = <0x021cd000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
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<&clks IMX6QDL_CLK_PRG1_AXI>;
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clock-names = "ipg", "axi";
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fsl,pres = <&pre4>, <&pre2>, <&pre3>;
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};
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};
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};
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};
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&fec {
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interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
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<0 119 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpc {
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compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
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};
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&ipu1 {
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compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
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fsl,prg = <&prg1>;
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};
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&ipu2 {
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compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
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fsl,prg = <&prg2>;
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};
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&ldb {
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clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel", "di2_sel", "di3_sel",
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"di0", "di1";
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};
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&mmdc0 {
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compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
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};
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&pcie {
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compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
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};
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