Marc Zyngier 4dfc050571 KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass ... Our GICv3 emulation always presents ICC_SRE_EL1 with DIB/DFB set to zero, which implies that there is a way to bypass the GIC and inject raw IRQ/FIQ by driving the CPU pins. Of course, we don't allow that when the GIC is configured, but we fail to indicate that to the guest. The obvious fix is to set these bits (and never let them being changed again). Reported-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2017-03-06 10:30:57 +00:00
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arm-gic-common.h	irqchip/gic-v3: Parse and export virtual GIC information	2016-05-03 12:54:21 +02:00
arm-gic-v3.h	KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass	2017-03-06 10:30:57 +00:00
arm-gic.h	irqchip/gic: Add platform driver for non-root GICs that require RPM	2016-06-13 11:53:52 +01:00
arm-vic.h	…
chained_irq.h	…
ingenic.h	MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip	2015-06-21 21:53:10 +02:00
irq-omap-intc.h	…
irq-partition-percpu.h	irqchip: Add per-cpu interrupt partitioning library	2016-05-02 13:42:51 +02:00
irq-sa11x0.h	ARM: 8367/1: sa1100: prepare for moving irq driver to drivers/irqchip	2015-05-28 14:40:03 +01:00
metag-ext.h	…
metag.h	…
mips-gic.h	clocksource: Use a plain u64 instead of cycle_t	2016-12-25 11:04:12 +01:00
mmp.h	…
mxs.h	…
versatile-fpga.h	…
xtensa-mx.h	…
xtensa-pic.h	…