Paul Walmsley 7b9487a9a5 clk: analogbits: add Wide-Range PLL library ... Add common library code for the Analog Bits Wide-Range PLL (WRPLL) IP block, as implemented in TSMC CLN28HPC. There is no bus interface or register target associated with this PLL. This library is intended to be used by drivers for IP blocks that expose registers connected to the PLL configuration and status signals. Based on code originally written by Wesley Terpstra <wesley@sifive.com>: 999529edf5 This version incorporates several changes requested by Stephen Boyd <sboyd@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Wesley Terpstra <wesley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Megan Wachs <megan@sifive.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org [sboyd@kernel.org: Fix some const issues] Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2019-05-03 09:20:48 -07:00
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analogbits-wrpll-cln28hpc.h	clk: analogbits: add Wide-Range PLL library	2019-05-03 09:20:48 -07:00
at91_pmc.h	ARM: at91: pm: add PMC fast startup registers defines	2018-07-17 15:08:07 +02:00
clk-conf.h	clk: Tag clk core files with SPDX	2018-12-11 09:57:47 -08:00
davinci.h	clk: davinci: Fix link errors when not all SoCs are enabled	2018-05-30 12:48:49 -07:00
mmp.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
mxs.h
renesas.h	clk: renesas: Convert to SPDX identifiers	2018-09-28 17:16:37 -07:00
sunxi-ng.h	clk: sunxi-ng: Add interface to query or configure MMC timing modes.	2017-08-30 14:01:47 +02:00
tegra.h	clk: tegra: MBIST work around for Tegra210	2018-03-08 19:18:08 +01:00
ti.h	clk: ti: add a usecount for autoidle	2019-02-15 16:47:55 +02:00
zynq.h	ARM: zynq: Map I/O memory on clkc init	2014-02-10 11:21:13 +01:00