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39bbf82d8c
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
31 lines
1.2 KiB
C
31 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_
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#define QCOM_PHY_QMP_PCS_USB_V6_H_
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/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
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#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4
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#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8
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#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc
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#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8
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#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
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#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90
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#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0
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#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
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#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc
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#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec
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#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
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#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
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#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
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#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
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#endif
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