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7bdc072086
As vendor document indicate, when REF_CLK bit set 0, then DP phy's REF_CLK should switch to 24M source clock. But due to IC PHY layout mistaken, some chips need to flip this bit(like RK3288), and unfortunately they didn't indicate in the DP version register. That's why we have to make this little hack. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
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* Analogix DP (Display Port) Core interface driver.
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*
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* Copyright (C) 2015 Rockchip Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ANALOGIX_DP_H_
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#define _ANALOGIX_DP_H_
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#include <drm/drm_crtc.h>
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enum analogix_dp_devtype {
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EXYNOS_DP,
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RK3288_DP,
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};
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static inline bool is_rockchip(enum analogix_dp_devtype type)
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{
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return type == RK3288_DP;
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}
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struct analogix_dp_plat_data {
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enum analogix_dp_devtype dev_type;
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struct drm_panel *panel;
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struct drm_encoder *encoder;
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struct drm_connector *connector;
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int (*power_on)(struct analogix_dp_plat_data *);
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int (*power_off)(struct analogix_dp_plat_data *);
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int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
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struct drm_connector *);
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int (*get_modes)(struct analogix_dp_plat_data *);
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};
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int analogix_dp_resume(struct device *dev);
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int analogix_dp_suspend(struct device *dev);
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int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
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struct analogix_dp_plat_data *plat_data);
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void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
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#endif /* _ANALOGIX_DP_H_ */
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