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c0d6fe2f01
As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here.) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWQT2WAAoJEIwa5zzehBx37tgQAIBe5eDJFXFihTlyOQ2plL3q vVH4OCzXIHELfM1J8CGZNah1wCQqNOts8RAmDCzxr+zSYuLOwJOEDZ6NKmErMxl0 NTj3+BsqKO3NRym970ofPqU9JRLQmpZ8K7dzk8Nwj2+r1WZHFu/j6Jv44n/Ns0lw 7+wxnG322lTm7SnvALCMD5lD4Y7VpThooWy5SdFtRoAetn+cLbVCJIeeQvO6Vxkp NooeJR0t2e8cpbAND5Jwu6eeWRcIbrvgjYDe0omhrIY05i9yNvIsC2HuQFGjF43z p2CnQvcKnhOXTZw3yse1Fx5igA7jqwVjjC/lVeDyxhusAtLpmuB6qbSaj7DpqkSQ nJxX1d49WKm68K+aknmee1kYRrvc4DE/kORI4IxXnsVNMu16ifTVLnxKgUhwzukb eZdTP6rsqgNozaYvh0k1vfSFd+CNSkBg+E9nrI3tU95yo3LOIhobVBCvBcWlmUvQ JdavRztqosChjIx3a9i1eCNKJtCg9p4m+gWjUqVVWsxBHe/3HojzjZnsBSynIQMA uGIVm0TKhNl1Svxl3oJo9257UCUK7+5PqJHK9IHrcWDULYx05JGSjuZcyvNS6Fo+ u1DMf0ud4gXJYhecFBa7b3zRjk5YxptgCCTjeEEOTUJbbhZqDjGFZlNuFi6dmqD3 ILJ2QMe/DGiPIlUmCfsx =qY1q -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
698 lines
17 KiB
Text
698 lines
17 KiB
Text
/*
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* Copyright (C) 2014 STMicroelectronics Limited.
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* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "stih407-pinctrl.dtsi"
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#include <dt-bindings/mfd/st-lpc.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/stih407-resets.h>
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#include <dt-bindings/interrupt-controller/irq-st.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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};
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};
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intc: interrupt-controller@08761000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x08761000 0x1000>, <0x08760100 0x100>;
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};
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scu@08760000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x08760000 0x1000>;
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};
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timer@08760200 {
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interrupt-parent = <&intc>;
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x08760200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&arm_periph_clk>;
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};
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l2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0x08762000 0x1000>;
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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cache-unified;
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cache-level = <2>;
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};
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arm-pmu {
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interrupt-parent = <&intc>;
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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pwm_regulator: pwm-regulator {
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compatible = "pwm-regulator";
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pwms = <&pwm1 3 8448>;
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regulator-name = "CPU_1V0_AVS";
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regulator-min-microvolt = <784000>;
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regulator-max-microvolt = <1299000>;
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regulator-always-on;
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max-duty-cycle = <255>;
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status = "okay";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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compatible = "simple-bus";
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restart {
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compatible = "st,stih407-restart";
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st,syscfg = <&syscfg_sbc_reg>;
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status = "okay";
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};
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powerdown: powerdown-controller {
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compatible = "st,stih407-powerdown";
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#reset-cells = <1>;
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};
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softreset: softreset-controller {
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compatible = "st,stih407-softreset";
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#reset-cells = <1>;
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};
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picophyreset: picophyreset-controller {
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compatible = "st,stih407-picophyreset";
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#reset-cells = <1>;
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};
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syscfg_sbc: sbc-syscfg@9620000 {
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compatible = "st,stih407-sbc-syscfg", "syscon";
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reg = <0x9620000 0x1000>;
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};
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syscfg_front: front-syscfg@9280000 {
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compatible = "st,stih407-front-syscfg", "syscon";
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reg = <0x9280000 0x1000>;
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};
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syscfg_rear: rear-syscfg@9290000 {
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compatible = "st,stih407-rear-syscfg", "syscon";
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reg = <0x9290000 0x1000>;
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};
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syscfg_flash: flash-syscfg@92a0000 {
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compatible = "st,stih407-flash-syscfg", "syscon";
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reg = <0x92a0000 0x1000>;
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};
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syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
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compatible = "st,stih407-sbc-reg-syscfg", "syscon";
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reg = <0x9600000 0x1000>;
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};
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syscfg_core: core-syscfg@92b0000 {
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compatible = "st,stih407-core-syscfg", "syscon";
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reg = <0x92b0000 0x1000>;
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};
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syscfg_lpm: lpm-syscfg@94b5100 {
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compatible = "st,stih407-lpm-syscfg", "syscon";
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reg = <0x94b5100 0x1000>;
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};
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irq-syscfg {
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compatible = "st,stih407-irq-syscfg";
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st,syscfg = <&syscfg_core>;
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st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
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<ST_IRQ_SYSCFG_PMU_1>;
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st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
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<ST_IRQ_SYSCFG_DISABLED>;
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};
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/* Display */
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vtg_main: sti-vtg-main@8d02800 {
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compatible = "st,vtg";
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reg = <0x8d02800 0x200>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
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};
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vtg_aux: sti-vtg-aux@8d00200 {
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compatible = "st,vtg";
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reg = <0x8d00200 0x100>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
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};
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serial@9830000 {
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compatible = "st,asc";
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reg = <0x9830000 0x2c>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial0>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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status = "disabled";
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};
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serial@9831000 {
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compatible = "st,asc";
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reg = <0x9831000 0x2c>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial1>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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status = "disabled";
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};
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serial@9832000 {
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compatible = "st,asc";
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reg = <0x9832000 0x2c>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial2>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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status = "disabled";
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};
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/* SBC_ASC0 - UART10 */
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sbc_serial0: serial@9530000 {
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compatible = "st,asc";
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reg = <0x9530000 0x2c>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_serial0>;
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clocks = <&clk_sysin>;
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status = "disabled";
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};
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serial@9531000 {
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compatible = "st,asc";
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reg = <0x9531000 0x2c>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_serial1>;
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clocks = <&clk_sysin>;
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status = "disabled";
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};
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i2c@9840000 {
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compatible = "st,comms-ssc4-i2c";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x9840000 0x110>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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status = "disabled";
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};
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i2c@9841000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9841000 0x110>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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status = "disabled";
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};
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i2c@9842000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9842000 0x110>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_default>;
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status = "disabled";
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};
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i2c@9843000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9843000 0x110>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3_default>;
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status = "disabled";
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};
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i2c@9844000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9844000 0x110>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4_default>;
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status = "disabled";
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};
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i2c@9845000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9845000 0x110>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c5_default>;
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status = "disabled";
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};
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/* SSCs on SBC */
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i2c@9540000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9540000 0x110>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_sysin>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c10_default>;
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status = "disabled";
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};
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i2c@9541000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9541000 0x110>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_sysin>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c11_default>;
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status = "disabled";
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};
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usb2_picophy0: phy1 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0x100 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY2_RESET>;
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reset-names = "global", "port";
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};
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miphy28lp_phy: miphy28lp@9b22000 {
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compatible = "st,miphy28lp-phy";
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st,syscfg = <&syscfg_core>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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phy_port0: port@9b22000 {
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reg = <0x9b22000 0xff>,
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<0x9b09000 0xff>,
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<0x9b04000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x114 0x818 0xe0 0xec>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
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};
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phy_port1: port@9b2a000 {
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reg = <0x9b2a000 0xff>,
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<0x9b19000 0xff>,
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<0x9b14000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x118 0x81c 0xe4 0xf0>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
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};
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phy_port2: port@8f95000 {
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reg = <0x8f95000 0xff>,
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<0x8f90000 0xff>;
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reg-names = "pipew",
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"usb3-up";
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st,syscfg = <0x11c 0x820>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
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};
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};
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spi@9840000 {
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compatible = "st,comms-ssc4-spi";
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reg = <0x9840000 0x110>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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pinctrl-0 = <&pinctrl_spi0_default>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi@9841000 {
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compatible = "st,comms-ssc4-spi";
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reg = <0x9841000 0x110>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default>;
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status = "disabled";
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};
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spi@9842000 {
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compatible = "st,comms-ssc4-spi";
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reg = <0x9842000 0x110>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi2_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9843000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9843000 0x110>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi3_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9844000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9844000 0x110>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi4_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SBC SSC */
|
|
spi@9540000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9540000 0x110>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi10_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9541000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9541000 0x110>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi11_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9542000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9542000 0x110>;
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi12_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: sdhci@09060000 {
|
|
compatible = "st,sdhci-stih407", "st,sdhci";
|
|
status = "disabled";
|
|
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
|
|
reg-names = "mmc", "top-mmc-delay";
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
|
|
interrupt-names = "mmcirq";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_mmc0>;
|
|
clock-names = "mmc";
|
|
clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
};
|
|
|
|
mmc1: sdhci@09080000 {
|
|
compatible = "st,sdhci-stih407", "st,sdhci";
|
|
status = "disabled";
|
|
reg = <0x09080000 0x7ff>;
|
|
reg-names = "mmc";
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
|
|
interrupt-names = "mmcirq";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sd1>;
|
|
clock-names = "mmc";
|
|
clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
|
|
resets = <&softreset STIH407_MMC1_SOFTRESET>;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
/* Watchdog and Real-Time Clock */
|
|
lpc@8787000 {
|
|
compatible = "st,stih407-lpc";
|
|
reg = <0x8787000 0x1000>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
|
|
timeout-sec = <120>;
|
|
st,syscfg = <&syscfg_core>;
|
|
st,lpc-mode = <ST_LPC_MODE_WDT>;
|
|
};
|
|
|
|
lpc@8788000 {
|
|
compatible = "st,stih407-lpc";
|
|
reg = <0x8788000 0x1000>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
|
|
st,lpc-mode = <ST_LPC_MODE_RTC>;
|
|
};
|
|
|
|
sata0: sata@9b20000 {
|
|
compatible = "st,ahci";
|
|
reg = <0x9b20000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
|
|
interrupt-names = "hostc";
|
|
|
|
phys = <&phy_port0 PHY_TYPE_SATA>;
|
|
phy-names = "ahci_phy";
|
|
|
|
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
|
|
<&softreset STIH407_SATA0_SOFTRESET>,
|
|
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
|
|
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
|
|
|
|
clock-names = "ahci_clk";
|
|
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sata1: sata@9b28000 {
|
|
compatible = "st,ahci";
|
|
reg = <0x9b28000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
|
|
interrupt-names = "hostc";
|
|
|
|
phys = <&phy_port1 PHY_TYPE_SATA>;
|
|
phy-names = "ahci_phy";
|
|
|
|
resets = <&powerdown STIH407_SATA1_POWERDOWN>,
|
|
<&softreset STIH407_SATA1_SOFTRESET>,
|
|
<&softreset STIH407_SATA1_PWR_SOFTRESET>;
|
|
reset-names = "pwr-dwn",
|
|
"sw-rst",
|
|
"pwr-rst";
|
|
|
|
clock-names = "ahci_clk";
|
|
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
st_dwc3: dwc3@8f94000 {
|
|
compatible = "st,stih407-dwc3";
|
|
reg = <0x08f94000 0x1000>, <0x110 0x4>;
|
|
reg-names = "reg-glue", "syscfg-reg";
|
|
st,syscfg = <&syscfg_core>;
|
|
resets = <&powerdown STIH407_USB3_POWERDOWN>,
|
|
<&softreset STIH407_MIPHY2_SOFTRESET>;
|
|
reset-names = "powerdown", "softreset";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb3>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
dwc3: dwc3@9900000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x09900000 0x100000>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
|
|
dr_mode = "host";
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
phys = <&usb2_picophy0>,
|
|
<&phy_port2 PHY_TYPE_USB3>;
|
|
};
|
|
};
|
|
|
|
/* COMMS PWM Module */
|
|
pwm0: pwm@9810000 {
|
|
compatible = "st,sti-pwm";
|
|
#pwm-cells = <2>;
|
|
reg = <0x9810000 0x68>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
|
|
clock-names = "pwm";
|
|
clocks = <&clk_sysin>;
|
|
st,pwm-num-chan = <1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SBC PWM Module */
|
|
pwm1: pwm@9510000 {
|
|
compatible = "st,sti-pwm";
|
|
#pwm-cells = <2>;
|
|
reg = <0x9510000 0x68>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1_chan0_default
|
|
&pinctrl_pwm1_chan1_default
|
|
&pinctrl_pwm1_chan2_default
|
|
&pinctrl_pwm1_chan3_default>;
|
|
clock-names = "pwm";
|
|
clocks = <&clk_sysin>;
|
|
st,pwm-num-chan = <4>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
rng10: rng@08a89000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a89000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
|
|
rng11: rng@08a8a000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a8a000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
|
|
ethernet0: dwmac@9630000 {
|
|
device_type = "network";
|
|
status = "disabled";
|
|
compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
|
|
reg = <0x9630000 0x8000>, <0x80 0x4>;
|
|
reg-names = "stmmaceth", "sti-ethconf";
|
|
|
|
st,syscon = <&syscfg_sbc_reg 0x80>;
|
|
st,gmac_en;
|
|
resets = <&softreset STIH407_ETH1_SOFTRESET>;
|
|
reset-names = "stmmaceth";
|
|
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
|
|
<GIC_SPI 99 IRQ_TYPE_NONE>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
|
|
/* DMA Bus Mode */
|
|
snps,pbl = <8>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_rgmii1>;
|
|
|
|
clock-names = "stmmaceth", "sti-ethclk";
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
|
|
<&clk_s_c0_flexgen CLK_ETH_PHY>;
|
|
};
|
|
|
|
rng10: rng@08a89000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a89000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
|
|
rng11: rng@08a8a000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a8a000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|