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![Shmulik Ravid](/assets/img/avatar_default.png)
This patch adds support to the bnx2x for retrieving dcb peer (remote) configuration from the embedded DCBX stack. Signed-off-by: Shmulik Ravid <shmulikr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1835 lines
52 KiB
C
1835 lines
52 KiB
C
/* bnx2x.h: Broadcom Everest network driver.
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*
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* Copyright (c) 2007-2011 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Based on code from Michael Chan's bnx2 driver
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*/
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#ifndef BNX2X_H
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#define BNX2X_H
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#include <linux/netdevice.h>
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#include <linux/types.h>
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/* compilation time flags */
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/* define this to make the driver freeze on error to allow getting debug info
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* (you will need to reboot afterwards) */
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/* #define BNX2X_STOP_ON_ERROR */
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#define DRV_MODULE_VERSION "1.62.12-0"
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#define DRV_MODULE_RELDATE "2011/03/20"
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#define BNX2X_BC_VER 0x040200
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#define BNX2X_MULTI_QUEUE
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#define BNX2X_NEW_NAPI
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#if defined(CONFIG_DCB)
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#define BCM_DCBNL
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#endif
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#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
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#define BCM_CNIC 1
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#include "../cnic_if.h"
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#endif
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#ifdef BCM_CNIC
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#define BNX2X_MIN_MSIX_VEC_CNT 3
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#define BNX2X_MSIX_VEC_FP_START 2
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#else
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#define BNX2X_MIN_MSIX_VEC_CNT 2
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#define BNX2X_MSIX_VEC_FP_START 1
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#endif
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#include <linux/mdio.h>
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#include <linux/pci.h>
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#include "bnx2x_reg.h"
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#include "bnx2x_fw_defs.h"
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#include "bnx2x_hsi.h"
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#include "bnx2x_link.h"
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#include "bnx2x_dcb.h"
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#include "bnx2x_stats.h"
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/* error/debug prints */
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#define DRV_MODULE_NAME "bnx2x"
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/* for messages that are currently off */
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#define BNX2X_MSG_OFF 0
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#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
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#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
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#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
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#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
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#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
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#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
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#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
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/* regular debug print */
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#define DP(__mask, __fmt, __args...) \
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do { \
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if (bp->msg_enable & (__mask)) \
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printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
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__func__, __LINE__, \
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bp->dev ? (bp->dev->name) : "?", \
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##__args); \
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} while (0)
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/* errors debug print */
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#define BNX2X_DBG_ERR(__fmt, __args...) \
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do { \
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if (netif_msg_probe(bp)) \
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pr_err("[%s:%d(%s)]" __fmt, \
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__func__, __LINE__, \
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bp->dev ? (bp->dev->name) : "?", \
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##__args); \
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} while (0)
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/* for errors (never masked) */
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#define BNX2X_ERR(__fmt, __args...) \
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do { \
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pr_err("[%s:%d(%s)]" __fmt, \
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__func__, __LINE__, \
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bp->dev ? (bp->dev->name) : "?", \
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##__args); \
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} while (0)
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#define BNX2X_ERROR(__fmt, __args...) do { \
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pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
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} while (0)
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/* before we have a dev->name use dev_info() */
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#define BNX2X_DEV_INFO(__fmt, __args...) \
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do { \
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if (netif_msg_probe(bp)) \
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dev_info(&bp->pdev->dev, __fmt, ##__args); \
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} while (0)
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void bnx2x_panic_dump(struct bnx2x *bp);
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#ifdef BNX2X_STOP_ON_ERROR
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#define bnx2x_panic() do { \
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bp->panic = 1; \
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BNX2X_ERR("driver assert\n"); \
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bnx2x_int_disable(bp); \
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bnx2x_panic_dump(bp); \
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} while (0)
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#else
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#define bnx2x_panic() do { \
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bp->panic = 1; \
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BNX2X_ERR("driver assert\n"); \
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bnx2x_panic_dump(bp); \
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} while (0)
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#endif
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#define bnx2x_mc_addr(ha) ((ha)->addr)
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#define bnx2x_uc_addr(ha) ((ha)->addr)
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#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
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#define U64_HI(x) (u32)(((u64)(x)) >> 32)
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#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
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#define REG_ADDR(bp, offset) ((bp->regview) + (offset))
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#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
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#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
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#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
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#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
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#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
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#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
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#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
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#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
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#define REG_RD_DMAE(bp, offset, valp, len32) \
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do { \
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bnx2x_read_dmae(bp, offset, len32);\
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memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
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} while (0)
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#define REG_WR_DMAE(bp, offset, valp, len32) \
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do { \
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memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
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bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
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offset, len32); \
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} while (0)
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#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
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REG_WR_DMAE(bp, offset, valp, len32)
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#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
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do { \
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memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
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bnx2x_write_big_buf_wb(bp, addr, len32); \
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} while (0)
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#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
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offsetof(struct shmem_region, field))
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#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
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#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
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#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
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offsetof(struct shmem2_region, field))
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#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
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#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
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#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
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offsetof(struct mf_cfg, field))
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#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
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offsetof(struct mf2_cfg, field))
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#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
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#define MF_CFG_WR(bp, field, val) REG_WR(bp,\
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MF_CFG_ADDR(bp, field), (val))
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#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
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#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
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(SHMEM2_RD((bp), size) > \
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offsetof(struct shmem2_region, field)))
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#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
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#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
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/* SP SB indices */
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/* General SP events - stats query, cfc delete, etc */
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#define HC_SP_INDEX_ETH_DEF_CONS 3
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/* EQ completions */
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#define HC_SP_INDEX_EQ_CONS 7
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/* FCoE L2 connection completions */
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#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
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#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
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/* iSCSI L2 */
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#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
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#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
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/* Special clients parameters */
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/* SB indices */
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/* FCoE L2 */
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#define BNX2X_FCOE_L2_RX_INDEX \
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(&bp->def_status_blk->sp_sb.\
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index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
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#define BNX2X_FCOE_L2_TX_INDEX \
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(&bp->def_status_blk->sp_sb.\
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index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
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/**
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* CIDs and CLIDs:
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* CLIDs below is a CLID for func 0, then the CLID for other
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* functions will be calculated by the formula:
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*
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* FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
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*
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*/
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/* iSCSI L2 */
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#define BNX2X_ISCSI_ETH_CL_ID 17
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#define BNX2X_ISCSI_ETH_CID 17
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/* FCoE L2 */
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#define BNX2X_FCOE_ETH_CL_ID 18
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#define BNX2X_FCOE_ETH_CID 18
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/** Additional rings budgeting */
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#ifdef BCM_CNIC
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#define CNIC_CONTEXT_USE 1
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#define FCOE_CONTEXT_USE 1
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#else
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#define CNIC_CONTEXT_USE 0
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#define FCOE_CONTEXT_USE 0
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#endif /* BCM_CNIC */
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#define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE)
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#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
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AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
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#define SM_RX_ID 0
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#define SM_TX_ID 1
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/* fast path */
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struct sw_rx_bd {
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struct sk_buff *skb;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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};
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struct sw_tx_bd {
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struct sk_buff *skb;
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u16 first_bd;
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u8 flags;
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/* Set on the first BD descriptor when there is a split BD */
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#define BNX2X_TSO_SPLIT_BD (1<<0)
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};
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struct sw_rx_page {
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struct page *page;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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};
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union db_prod {
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struct doorbell_set_prod data;
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u32 raw;
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};
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/* MC hsi */
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#define BCM_PAGE_SHIFT 12
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#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
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#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
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#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
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#define PAGES_PER_SGE_SHIFT 0
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#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
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#define SGE_PAGE_SIZE PAGE_SIZE
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#define SGE_PAGE_SHIFT PAGE_SHIFT
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#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
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/* SGE ring related macros */
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#define NUM_RX_SGE_PAGES 2
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#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
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#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
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/* RX_SGE_CNT is promised to be a power of 2 */
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#define RX_SGE_MASK (RX_SGE_CNT - 1)
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#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
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#define MAX_RX_SGE (NUM_RX_SGE - 1)
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#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
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(MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
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#define RX_SGE(x) ((x) & MAX_RX_SGE)
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/* SGE producer mask related macros */
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/* Number of bits in one sge_mask array element */
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#define RX_SGE_MASK_ELEM_SZ 64
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#define RX_SGE_MASK_ELEM_SHIFT 6
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#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
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/* Creates a bitmask of all ones in less significant bits.
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idx - index of the most significant bit in the created mask */
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#define RX_SGE_ONES_MASK(idx) \
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(((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
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#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
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/* Number of u64 elements in SGE mask array */
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#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
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RX_SGE_MASK_ELEM_SZ)
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#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
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#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
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union host_hc_status_block {
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/* pointer to fp status block e1x */
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struct host_hc_status_block_e1x *e1x_sb;
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/* pointer to fp status block e2 */
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struct host_hc_status_block_e2 *e2_sb;
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};
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struct bnx2x_fastpath {
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#define BNX2X_NAPI_WEIGHT 128
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struct napi_struct napi;
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union host_hc_status_block status_blk;
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/* chip independed shortcuts into sb structure */
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__le16 *sb_index_values;
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__le16 *sb_running_index;
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/* chip independed shortcut into rx_prods_offset memory */
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u32 ustorm_rx_prods_offset;
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u32 rx_buf_size;
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dma_addr_t status_blk_mapping;
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struct sw_tx_bd *tx_buf_ring;
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union eth_tx_bd_types *tx_desc_ring;
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dma_addr_t tx_desc_mapping;
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struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
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struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
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struct eth_rx_bd *rx_desc_ring;
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dma_addr_t rx_desc_mapping;
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union eth_rx_cqe *rx_comp_ring;
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dma_addr_t rx_comp_mapping;
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/* SGE ring */
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struct eth_rx_sge *rx_sge_ring;
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dma_addr_t rx_sge_mapping;
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u64 sge_mask[RX_SGE_MASK_LEN];
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int state;
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#define BNX2X_FP_STATE_CLOSED 0
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#define BNX2X_FP_STATE_IRQ 0x80000
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#define BNX2X_FP_STATE_OPENING 0x90000
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#define BNX2X_FP_STATE_OPEN 0xa0000
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#define BNX2X_FP_STATE_HALTING 0xb0000
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#define BNX2X_FP_STATE_HALTED 0xc0000
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#define BNX2X_FP_STATE_TERMINATING 0xd0000
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#define BNX2X_FP_STATE_TERMINATED 0xe0000
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u8 index; /* number in fp array */
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u8 cl_id; /* eth client id */
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u8 cl_qzone_id;
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u8 fw_sb_id; /* status block number in FW */
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u8 igu_sb_id; /* status block number in HW */
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u32 cid;
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union db_prod tx_db;
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u16 tx_pkt_prod;
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u16 tx_pkt_cons;
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u16 tx_bd_prod;
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u16 tx_bd_cons;
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__le16 *tx_cons_sb;
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__le16 fp_hc_idx;
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u16 rx_bd_prod;
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u16 rx_bd_cons;
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u16 rx_comp_prod;
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u16 rx_comp_cons;
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u16 rx_sge_prod;
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/* The last maximal completed SGE */
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u16 last_max_sge;
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__le16 *rx_cons_sb;
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unsigned long tx_pkt,
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rx_pkt,
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rx_calls;
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/* TPA related */
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struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
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u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
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#define BNX2X_TPA_START 1
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#define BNX2X_TPA_STOP 2
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u8 disable_tpa;
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#ifdef BNX2X_STOP_ON_ERROR
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u64 tpa_queue_used;
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#endif
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struct tstorm_per_client_stats old_tclient;
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struct ustorm_per_client_stats old_uclient;
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struct xstorm_per_client_stats old_xclient;
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struct bnx2x_eth_q_stats eth_q_stats;
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/* The size is calculated using the following:
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sizeof name field from netdev structure +
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4 ('-Xx-' string) +
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4 (for the digits and to make it DWORD aligned) */
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#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
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char name[FP_NAME_SIZE];
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struct bnx2x *bp; /* parent */
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};
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#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
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/* Use 2500 as a mini-jumbo MTU for FCoE */
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#define BNX2X_FCOE_MINI_JUMBO_MTU 2500
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#ifdef BCM_CNIC
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/* FCoE L2 `fastpath' is right after the eth entries */
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#define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
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#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
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#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
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#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
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#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
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#else
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#define IS_FCOE_FP(fp) false
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#define IS_FCOE_IDX(idx) false
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#endif
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/* MC hsi */
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#define MAX_FETCH_BD 13 /* HW max BDs per packet */
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#define RX_COPY_THRESH 92
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#define NUM_TX_RINGS 16
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#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
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#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
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#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
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#define MAX_TX_BD (NUM_TX_BD - 1)
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#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
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#define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL
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#define INIT_TX_RING_SIZE MAX_TX_AVAIL
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#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
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(MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
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#define TX_BD(x) ((x) & MAX_TX_BD)
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#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
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/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
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#define NUM_RX_RINGS 8
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#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
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#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
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#define RX_DESC_MASK (RX_DESC_CNT - 1)
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#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
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#define MAX_RX_BD (NUM_RX_BD - 1)
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#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
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#define MIN_RX_SIZE_TPA 72
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#define MIN_RX_SIZE_NONTPA 10
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#define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL
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#define INIT_RX_RING_SIZE MAX_RX_AVAIL
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#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
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(MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
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#define RX_BD(x) ((x) & MAX_RX_BD)
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/* As long as CQE is 4 times bigger than BD entry we have to allocate
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4 times more pages for CQ ring in order to keep it balanced with
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BD ring */
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#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
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#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
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#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
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#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
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#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
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#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
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#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
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(MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
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#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
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/* This is needed for determining of last_max */
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#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
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#define __SGE_MASK_SET_BIT(el, bit) \
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do { \
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el = ((el) | ((u64)0x1 << (bit))); \
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} while (0)
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#define __SGE_MASK_CLEAR_BIT(el, bit) \
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do { \
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el = ((el) & (~((u64)0x1 << (bit)))); \
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} while (0)
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#define SGE_MASK_SET_BIT(fp, idx) \
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__SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
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((idx) & RX_SGE_MASK_ELEM_MASK))
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#define SGE_MASK_CLEAR_BIT(fp, idx) \
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__SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
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((idx) & RX_SGE_MASK_ELEM_MASK))
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/* used on a CID received from the HW */
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#define SW_CID(x) (le32_to_cpu(x) & \
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(COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
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#define CQE_CMD(x) (le32_to_cpu(x) >> \
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COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
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#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
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le32_to_cpu((bd)->addr_lo))
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#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
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#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
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#define BNX2X_DB_SHIFT 7 /* 128 bytes*/
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#define DPM_TRIGER_TYPE 0x40
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#define DOORBELL(bp, cid, val) \
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do { \
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writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
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DPM_TRIGER_TYPE); \
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} while (0)
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/* TX CSUM helpers */
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#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
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skb->csum_offset)
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#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
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skb->csum_offset))
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#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
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#define XMIT_PLAIN 0
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#define XMIT_CSUM_V4 0x1
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#define XMIT_CSUM_V6 0x2
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#define XMIT_CSUM_TCP 0x4
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#define XMIT_GSO_V4 0x8
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#define XMIT_GSO_V6 0x10
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#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
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#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
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/* stuff added to make the code fit 80Col */
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#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
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#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
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#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
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#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
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(TPA_TYPE_START | TPA_TYPE_END))
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#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
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#define BNX2X_IP_CSUM_ERR(cqe) \
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(!((cqe)->fast_path_cqe.status_flags & \
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ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
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((cqe)->fast_path_cqe.type_error_flags & \
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ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
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#define BNX2X_L4_CSUM_ERR(cqe) \
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(!((cqe)->fast_path_cqe.status_flags & \
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ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
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((cqe)->fast_path_cqe.type_error_flags & \
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ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
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#define BNX2X_RX_CSUM_OK(cqe) \
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(!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
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#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
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(((le16_to_cpu(flags) & \
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PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
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PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
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== PRS_FLAG_OVERETH_IPV4)
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#define BNX2X_RX_SUM_FIX(cqe) \
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BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
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#define U_SB_ETH_RX_CQ_INDEX 1
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#define U_SB_ETH_RX_BD_INDEX 2
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#define C_SB_ETH_TX_CQ_INDEX 5
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#define BNX2X_RX_SB_INDEX \
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(&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX])
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#define BNX2X_TX_SB_INDEX \
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(&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
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/* end of fast path */
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/* common */
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struct bnx2x_common {
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u32 chip_id;
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/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
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#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
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#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
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#define CHIP_NUM_57710 0x164e
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#define CHIP_NUM_57711 0x164f
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#define CHIP_NUM_57711E 0x1650
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#define CHIP_NUM_57712 0x1662
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#define CHIP_NUM_57712E 0x1663
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#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
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#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
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#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
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#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
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#define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E)
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#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
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CHIP_IS_57711E(bp))
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#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
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CHIP_IS_57712E(bp))
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#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
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#define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp))
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#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
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#define CHIP_REV_Ax 0x00000000
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/* assume maximum 5 revisions */
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#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
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/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
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#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
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!(CHIP_REV(bp) & 0x00001000))
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/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
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#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
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(CHIP_REV(bp) & 0x00001000))
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#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
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((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
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#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
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#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
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#define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
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|
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int flash_size;
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#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
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#define NVRAM_TIMEOUT_COUNT 30000
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#define NVRAM_PAGE_SIZE 256
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u32 shmem_base;
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u32 shmem2_base;
|
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u32 mf_cfg_base;
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u32 mf2_cfg_base;
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|
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u32 hw_config;
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|
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u32 bc_ver;
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|
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u8 int_block;
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#define INT_BLOCK_HC 0
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#define INT_BLOCK_IGU 1
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#define INT_BLOCK_MODE_NORMAL 0
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#define INT_BLOCK_MODE_BW_COMP 2
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#define CHIP_INT_MODE_IS_NBC(bp) \
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(CHIP_IS_E2(bp) && \
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!((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
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#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
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u8 chip_port_mode;
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#define CHIP_4_PORT_MODE 0x0
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#define CHIP_2_PORT_MODE 0x1
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#define CHIP_PORT_MODE_NONE 0x2
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#define CHIP_MODE(bp) (bp->common.chip_port_mode)
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#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
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};
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/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
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#define BNX2X_IGU_STAS_MSG_VF_CNT 64
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#define BNX2X_IGU_STAS_MSG_PF_CNT 4
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/* end of common */
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/* port */
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struct bnx2x_port {
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u32 pmf;
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u32 link_config[LINK_CONFIG_SIZE];
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u32 supported[LINK_CONFIG_SIZE];
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/* link settings - missing defines */
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#define SUPPORTED_2500baseX_Full (1 << 15)
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u32 advertising[LINK_CONFIG_SIZE];
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/* link settings - missing defines */
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#define ADVERTISED_2500baseX_Full (1 << 15)
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u32 phy_addr;
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|
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/* used to synchronize phy accesses */
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struct mutex phy_mutex;
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int need_hw_lock;
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u32 port_stx;
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struct nig_stats old_nig_stats;
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};
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/* end of port */
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/* e1h Classification CAM line allocations */
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enum {
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CAM_ETH_LINE = 0,
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CAM_ISCSI_ETH_LINE,
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CAM_FIP_ETH_LINE,
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CAM_FIP_MCAST_LINE,
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CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE
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};
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/* number of MACs per function in NIG memory - used for SI mode */
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#define NIG_LLH_FUNC_MEM_SIZE 16
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/* number of entries in NIG_REG_LLHX_FUNC_MEM */
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#define NIG_LLH_FUNC_MEM_MAX_OFFSET 8
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#define BNX2X_VF_ID_INVALID 0xFF
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|
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/*
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* The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
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* control by the number of fast-path status blocks supported by the
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* device (HW/FW). Each fast-path status block (FP-SB) aka non-default
|
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* status block represents an independent interrupts context that can
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* serve a regular L2 networking queue. However special L2 queues such
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* as the FCoE queue do not require a FP-SB and other components like
|
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* the CNIC may consume FP-SB reducing the number of possible L2 queues
|
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*
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* If the maximum number of FP-SB available is X then:
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* a. If CNIC is supported it consumes 1 FP-SB thus the max number of
|
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* regular L2 queues is Y=X-1
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* b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
|
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* c. If the FCoE L2 queue is supported the actual number of L2 queues
|
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* is Y+1
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* d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
|
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* slow-path interrupts) or Y+2 if CNIC is supported (one additional
|
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* FP interrupt context for the CNIC).
|
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* e. The number of HW context (CID count) is always X or X+1 if FCoE
|
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* L2 queue is supported. the cid for the FCoE L2 queue is always X.
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*/
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#define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */
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#define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */
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|
|
/*
|
|
* cid_cnt paramter below refers to the value returned by
|
|
* 'bnx2x_get_l2_cid_count()' routine
|
|
*/
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|
|
|
/*
|
|
* The number of FP context allocated by the driver == max number of regular
|
|
* L2 queues + 1 for the FCoE L2 queue
|
|
*/
|
|
#define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
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|
|
/*
|
|
* The number of FP-SB allocated by the driver == max number of regular L2
|
|
* queues + 1 for the CNIC which also consumes an FP-SB
|
|
*/
|
|
#define FP_SB_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE)
|
|
#define NUM_IGU_SB_REQUIRED(cid_cnt) \
|
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(FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE)
|
|
|
|
union cdu_context {
|
|
struct eth_context eth;
|
|
char pad[1024];
|
|
};
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|
|
|
/* CDU host DB constants */
|
|
#define CDU_ILT_PAGE_SZ_HW 3
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|
#define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
|
|
#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
|
|
|
|
#ifdef BCM_CNIC
|
|
#define CNIC_ISCSI_CID_MAX 256
|
|
#define CNIC_FCOE_CID_MAX 2048
|
|
#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
|
|
#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
|
|
#endif
|
|
|
|
#define QM_ILT_PAGE_SZ_HW 3
|
|
#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */
|
|
#define QM_CID_ROUND 1024
|
|
|
|
#ifdef BCM_CNIC
|
|
/* TM (timers) host DB constants */
|
|
#define TM_ILT_PAGE_SZ_HW 2
|
|
#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */
|
|
/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
|
|
#define TM_CONN_NUM 1024
|
|
#define TM_ILT_SZ (8 * TM_CONN_NUM)
|
|
#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
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|
|
|
/* SRC (Searcher) host DB constants */
|
|
#define SRC_ILT_PAGE_SZ_HW 3
|
|
#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */
|
|
#define SRC_HASH_BITS 10
|
|
#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
|
|
#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
|
|
#define SRC_T2_SZ SRC_ILT_SZ
|
|
#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
|
|
#endif
|
|
|
|
#define MAX_DMAE_C 8
|
|
|
|
/* DMA memory not used in fastpath */
|
|
struct bnx2x_slowpath {
|
|
struct eth_stats_query fw_stats;
|
|
struct mac_configuration_cmd mac_config;
|
|
struct mac_configuration_cmd mcast_config;
|
|
struct mac_configuration_cmd uc_mac_config;
|
|
struct client_init_ramrod_data client_init_data;
|
|
|
|
/* used by dmae command executer */
|
|
struct dmae_command dmae[MAX_DMAE_C];
|
|
|
|
u32 stats_comp;
|
|
union mac_stats mac_stats;
|
|
struct nig_stats nig_stats;
|
|
struct host_port_stats port_stats;
|
|
struct host_func_stats func_stats;
|
|
struct host_func_stats func_stats_base;
|
|
|
|
u32 wb_comp;
|
|
u32 wb_data[4];
|
|
/* pfc configuration for DCBX ramrod */
|
|
struct flow_control_configuration pfc_config;
|
|
};
|
|
|
|
#define bnx2x_sp(bp, var) (&bp->slowpath->var)
|
|
#define bnx2x_sp_mapping(bp, var) \
|
|
(bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
|
|
|
|
|
|
/* attn group wiring */
|
|
#define MAX_DYNAMIC_ATTN_GRPS 8
|
|
|
|
struct attn_route {
|
|
u32 sig[5];
|
|
};
|
|
|
|
struct iro {
|
|
u32 base;
|
|
u16 m1;
|
|
u16 m2;
|
|
u16 m3;
|
|
u16 size;
|
|
};
|
|
|
|
struct hw_context {
|
|
union cdu_context *vcxt;
|
|
dma_addr_t cxt_mapping;
|
|
size_t size;
|
|
};
|
|
|
|
/* forward */
|
|
struct bnx2x_ilt;
|
|
|
|
typedef enum {
|
|
BNX2X_RECOVERY_DONE,
|
|
BNX2X_RECOVERY_INIT,
|
|
BNX2X_RECOVERY_WAIT,
|
|
} bnx2x_recovery_state_t;
|
|
|
|
/**
|
|
* Event queue (EQ or event ring) MC hsi
|
|
* NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
|
|
*/
|
|
#define NUM_EQ_PAGES 1
|
|
#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
|
|
#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
|
|
#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
|
|
#define EQ_DESC_MASK (NUM_EQ_DESC - 1)
|
|
#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
|
|
|
|
/* depends on EQ_DESC_CNT_PAGE being a power of 2 */
|
|
#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
|
|
(EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
|
|
|
|
/* depends on the above and on NUM_EQ_PAGES being a power of 2 */
|
|
#define EQ_DESC(x) ((x) & EQ_DESC_MASK)
|
|
|
|
#define BNX2X_EQ_INDEX \
|
|
(&bp->def_status_blk->sp_sb.\
|
|
index_values[HC_SP_INDEX_EQ_CONS])
|
|
|
|
/* This is a data that will be used to create a link report message.
|
|
* We will keep the data used for the last link report in order
|
|
* to prevent reporting the same link parameters twice.
|
|
*/
|
|
struct bnx2x_link_report_data {
|
|
u16 line_speed; /* Effective line speed */
|
|
unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
|
|
};
|
|
|
|
enum {
|
|
BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
|
|
BNX2X_LINK_REPORT_LINK_DOWN,
|
|
BNX2X_LINK_REPORT_RX_FC_ON,
|
|
BNX2X_LINK_REPORT_TX_FC_ON,
|
|
};
|
|
|
|
struct bnx2x {
|
|
/* Fields used in the tx and intr/napi performance paths
|
|
* are grouped together in the beginning of the structure
|
|
*/
|
|
struct bnx2x_fastpath *fp;
|
|
void __iomem *regview;
|
|
void __iomem *doorbells;
|
|
u16 db_size;
|
|
|
|
struct net_device *dev;
|
|
struct pci_dev *pdev;
|
|
|
|
struct iro *iro_arr;
|
|
#define IRO (bp->iro_arr)
|
|
|
|
atomic_t intr_sem;
|
|
|
|
bnx2x_recovery_state_t recovery_state;
|
|
int is_leader;
|
|
struct msix_entry *msix_table;
|
|
#define INT_MODE_INTx 1
|
|
#define INT_MODE_MSI 2
|
|
|
|
int tx_ring_size;
|
|
|
|
/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
|
|
#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
|
|
#define ETH_MIN_PACKET_SIZE 60
|
|
#define ETH_MAX_PACKET_SIZE 1500
|
|
#define ETH_MAX_JUMBO_PACKET_SIZE 9600
|
|
|
|
/* Max supported alignment is 256 (8 shift) */
|
|
#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
|
|
L1_CACHE_SHIFT : 8)
|
|
#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
|
|
#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
|
|
|
|
struct host_sp_status_block *def_status_blk;
|
|
#define DEF_SB_IGU_ID 16
|
|
#define DEF_SB_ID HC_SP_SB_ID
|
|
__le16 def_idx;
|
|
__le16 def_att_idx;
|
|
u32 attn_state;
|
|
struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
|
|
|
|
/* slow path ring */
|
|
struct eth_spe *spq;
|
|
dma_addr_t spq_mapping;
|
|
u16 spq_prod_idx;
|
|
struct eth_spe *spq_prod_bd;
|
|
struct eth_spe *spq_last_bd;
|
|
__le16 *dsb_sp_prod;
|
|
atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
|
|
/* used to synchronize spq accesses */
|
|
spinlock_t spq_lock;
|
|
|
|
/* event queue */
|
|
union event_ring_elem *eq_ring;
|
|
dma_addr_t eq_mapping;
|
|
u16 eq_prod;
|
|
u16 eq_cons;
|
|
__le16 *eq_cons_sb;
|
|
atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
|
|
|
|
/* Flags for marking that there is a STAT_QUERY or
|
|
SET_MAC ramrod pending */
|
|
int stats_pending;
|
|
int set_mac_pending;
|
|
|
|
/* End of fields used in the performance code paths */
|
|
|
|
int panic;
|
|
int msg_enable;
|
|
|
|
u32 flags;
|
|
#define PCIX_FLAG 1
|
|
#define PCI_32BIT_FLAG 2
|
|
#define ONE_PORT_FLAG 4
|
|
#define NO_WOL_FLAG 8
|
|
#define USING_DAC_FLAG 0x10
|
|
#define USING_MSIX_FLAG 0x20
|
|
#define USING_MSI_FLAG 0x40
|
|
|
|
#define TPA_ENABLE_FLAG 0x80
|
|
#define NO_MCP_FLAG 0x100
|
|
#define DISABLE_MSI_FLAG 0x200
|
|
#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
|
|
#define MF_FUNC_DIS 0x1000
|
|
#define FCOE_MACS_SET 0x2000
|
|
#define NO_FCOE_FLAG 0x4000
|
|
#define NO_ISCSI_OOO_FLAG 0x8000
|
|
#define NO_ISCSI_FLAG 0x10000
|
|
|
|
#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
|
|
#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
|
|
#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
|
|
|
|
int pf_num; /* absolute PF number */
|
|
int pfid; /* per-path PF number */
|
|
int base_fw_ndsb;
|
|
#define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \
|
|
0 : (bp->pf_num & 1))
|
|
#define BP_PORT(bp) (bp->pfid & 1)
|
|
#define BP_FUNC(bp) (bp->pfid)
|
|
#define BP_ABS_FUNC(bp) (bp->pf_num)
|
|
#define BP_E1HVN(bp) (bp->pfid >> 1)
|
|
#define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \
|
|
0 : BP_E1HVN(bp))
|
|
#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
|
|
#define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
|
|
BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1))
|
|
|
|
#ifdef BCM_CNIC
|
|
#define BCM_CNIC_CID_START 16
|
|
#define BCM_ISCSI_ETH_CL_ID 17
|
|
#endif
|
|
|
|
int pm_cap;
|
|
int pcie_cap;
|
|
int mrrs;
|
|
|
|
struct delayed_work sp_task;
|
|
struct delayed_work reset_task;
|
|
struct timer_list timer;
|
|
int current_interval;
|
|
|
|
u16 fw_seq;
|
|
u16 fw_drv_pulse_wr_seq;
|
|
u32 func_stx;
|
|
|
|
struct link_params link_params;
|
|
struct link_vars link_vars;
|
|
u32 link_cnt;
|
|
struct bnx2x_link_report_data last_reported_link;
|
|
|
|
struct mdio_if_info mdio;
|
|
|
|
struct bnx2x_common common;
|
|
struct bnx2x_port port;
|
|
|
|
struct cmng_struct_per_port cmng;
|
|
u32 vn_weight_sum;
|
|
|
|
u32 mf_config[E1HVN_MAX];
|
|
u32 mf2_config[E2_FUNC_MAX];
|
|
u16 mf_ov;
|
|
u8 mf_mode;
|
|
#define IS_MF(bp) (bp->mf_mode != 0)
|
|
#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
|
|
#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
|
|
|
|
u8 wol;
|
|
|
|
int rx_ring_size;
|
|
|
|
u16 tx_quick_cons_trip_int;
|
|
u16 tx_quick_cons_trip;
|
|
u16 tx_ticks_int;
|
|
u16 tx_ticks;
|
|
|
|
u16 rx_quick_cons_trip_int;
|
|
u16 rx_quick_cons_trip;
|
|
u16 rx_ticks_int;
|
|
u16 rx_ticks;
|
|
/* Maximal coalescing timeout in us */
|
|
#define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
|
|
|
|
u32 lin_cnt;
|
|
|
|
int state;
|
|
#define BNX2X_STATE_CLOSED 0
|
|
#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
|
|
#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
|
|
#define BNX2X_STATE_OPEN 0x3000
|
|
#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
|
|
#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
|
|
#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
|
|
#define BNX2X_STATE_FUNC_STARTED 0x7000
|
|
#define BNX2X_STATE_DIAG 0xe000
|
|
#define BNX2X_STATE_ERROR 0xf000
|
|
|
|
int multi_mode;
|
|
int num_queues;
|
|
int disable_tpa;
|
|
int int_mode;
|
|
u32 *rx_indir_table;
|
|
|
|
struct tstorm_eth_mac_filter_config mac_filters;
|
|
#define BNX2X_ACCEPT_NONE 0x0000
|
|
#define BNX2X_ACCEPT_UNICAST 0x0001
|
|
#define BNX2X_ACCEPT_MULTICAST 0x0002
|
|
#define BNX2X_ACCEPT_ALL_UNICAST 0x0004
|
|
#define BNX2X_ACCEPT_ALL_MULTICAST 0x0008
|
|
#define BNX2X_ACCEPT_BROADCAST 0x0010
|
|
#define BNX2X_ACCEPT_UNMATCHED_UCAST 0x0020
|
|
#define BNX2X_PROMISCUOUS_MODE 0x10000
|
|
|
|
u32 rx_mode;
|
|
#define BNX2X_RX_MODE_NONE 0
|
|
#define BNX2X_RX_MODE_NORMAL 1
|
|
#define BNX2X_RX_MODE_ALLMULTI 2
|
|
#define BNX2X_RX_MODE_PROMISC 3
|
|
#define BNX2X_MAX_MULTICAST 64
|
|
#define BNX2X_MAX_EMUL_MULTI 16
|
|
|
|
u8 igu_dsb_id;
|
|
u8 igu_base_sb;
|
|
u8 igu_sb_cnt;
|
|
dma_addr_t def_status_blk_mapping;
|
|
|
|
struct bnx2x_slowpath *slowpath;
|
|
dma_addr_t slowpath_mapping;
|
|
struct hw_context context;
|
|
|
|
struct bnx2x_ilt *ilt;
|
|
#define BP_ILT(bp) ((bp)->ilt)
|
|
#define ILT_MAX_LINES 128
|
|
|
|
int l2_cid_count;
|
|
#define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
|
|
ILT_PAGE_CIDS))
|
|
#define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
|
|
|
|
int qm_cid_count;
|
|
|
|
int dropless_fc;
|
|
|
|
#ifdef BCM_CNIC
|
|
u32 cnic_flags;
|
|
#define BNX2X_CNIC_FLAG_MAC_SET 1
|
|
void *t2;
|
|
dma_addr_t t2_mapping;
|
|
struct cnic_ops __rcu *cnic_ops;
|
|
void *cnic_data;
|
|
u32 cnic_tag;
|
|
struct cnic_eth_dev cnic_eth_dev;
|
|
union host_hc_status_block cnic_sb;
|
|
dma_addr_t cnic_sb_mapping;
|
|
#define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp))
|
|
#define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb)
|
|
struct eth_spe *cnic_kwq;
|
|
struct eth_spe *cnic_kwq_prod;
|
|
struct eth_spe *cnic_kwq_cons;
|
|
struct eth_spe *cnic_kwq_last;
|
|
u16 cnic_kwq_pending;
|
|
u16 cnic_spq_pending;
|
|
struct mutex cnic_mutex;
|
|
u8 fip_mac[ETH_ALEN];
|
|
#endif
|
|
|
|
int dmae_ready;
|
|
/* used to synchronize dmae accesses */
|
|
spinlock_t dmae_lock;
|
|
|
|
/* used to protect the FW mail box */
|
|
struct mutex fw_mb_mutex;
|
|
|
|
/* used to synchronize stats collecting */
|
|
int stats_state;
|
|
|
|
/* used for synchronization of concurrent threads statistics handling */
|
|
spinlock_t stats_lock;
|
|
|
|
/* used by dmae command loader */
|
|
struct dmae_command stats_dmae;
|
|
int executer_idx;
|
|
|
|
u16 stats_counter;
|
|
struct bnx2x_eth_stats eth_stats;
|
|
|
|
struct z_stream_s *strm;
|
|
void *gunzip_buf;
|
|
dma_addr_t gunzip_mapping;
|
|
int gunzip_outlen;
|
|
#define FW_BUF_SIZE 0x8000
|
|
#define GUNZIP_BUF(bp) (bp->gunzip_buf)
|
|
#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
|
|
#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
|
|
|
|
struct raw_op *init_ops;
|
|
/* Init blocks offsets inside init_ops */
|
|
u16 *init_ops_offsets;
|
|
/* Data blob - has 32 bit granularity */
|
|
u32 *init_data;
|
|
/* Zipped PRAM blobs - raw data */
|
|
const u8 *tsem_int_table_data;
|
|
const u8 *tsem_pram_data;
|
|
const u8 *usem_int_table_data;
|
|
const u8 *usem_pram_data;
|
|
const u8 *xsem_int_table_data;
|
|
const u8 *xsem_pram_data;
|
|
const u8 *csem_int_table_data;
|
|
const u8 *csem_pram_data;
|
|
#define INIT_OPS(bp) (bp->init_ops)
|
|
#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
|
|
#define INIT_DATA(bp) (bp->init_data)
|
|
#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
|
|
#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
|
|
#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
|
|
#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
|
|
#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
|
|
#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
|
|
#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
|
|
#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
|
|
|
|
char fw_ver[32];
|
|
const struct firmware *firmware;
|
|
/* LLDP params */
|
|
struct bnx2x_config_lldp_params lldp_config_params;
|
|
|
|
/* DCB support on/off */
|
|
u16 dcb_state;
|
|
#define BNX2X_DCB_STATE_OFF 0
|
|
#define BNX2X_DCB_STATE_ON 1
|
|
|
|
/* DCBX engine mode */
|
|
int dcbx_enabled;
|
|
#define BNX2X_DCBX_ENABLED_OFF 0
|
|
#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
|
|
#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
|
|
#define BNX2X_DCBX_ENABLED_INVALID (-1)
|
|
|
|
bool dcbx_mode_uset;
|
|
|
|
struct bnx2x_config_dcbx_params dcbx_config_params;
|
|
|
|
struct bnx2x_dcbx_port_params dcbx_port_params;
|
|
int dcb_version;
|
|
|
|
/* DCBX Negotiation results */
|
|
struct dcbx_features dcbx_local_feat;
|
|
u32 dcbx_error;
|
|
#ifdef BCM_DCBNL
|
|
struct dcbx_features dcbx_remote_feat;
|
|
u32 dcbx_remote_flags;
|
|
#endif
|
|
u32 pending_max;
|
|
};
|
|
|
|
/**
|
|
* Init queue/func interface
|
|
*/
|
|
/* queue init flags */
|
|
#define QUEUE_FLG_TPA 0x0001
|
|
#define QUEUE_FLG_CACHE_ALIGN 0x0002
|
|
#define QUEUE_FLG_STATS 0x0004
|
|
#define QUEUE_FLG_OV 0x0008
|
|
#define QUEUE_FLG_VLAN 0x0010
|
|
#define QUEUE_FLG_COS 0x0020
|
|
#define QUEUE_FLG_HC 0x0040
|
|
#define QUEUE_FLG_DHC 0x0080
|
|
#define QUEUE_FLG_OOO 0x0100
|
|
|
|
#define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR
|
|
#define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR
|
|
#define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0
|
|
#define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR
|
|
|
|
|
|
|
|
/* rss capabilities */
|
|
#define RSS_IPV4_CAP 0x0001
|
|
#define RSS_IPV4_TCP_CAP 0x0002
|
|
#define RSS_IPV6_CAP 0x0004
|
|
#define RSS_IPV6_TCP_CAP 0x0008
|
|
|
|
#define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
|
|
#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE)
|
|
|
|
/* ethtool statistics are displayed for all regular ethernet queues and the
|
|
* fcoe L2 queue if not disabled
|
|
*/
|
|
#define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \
|
|
(BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE))
|
|
|
|
#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
|
|
|
|
#define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
|
|
|
|
#define RSS_IPV4_CAP_MASK \
|
|
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
|
|
|
|
#define RSS_IPV4_TCP_CAP_MASK \
|
|
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
|
|
|
|
#define RSS_IPV6_CAP_MASK \
|
|
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
|
|
|
|
#define RSS_IPV6_TCP_CAP_MASK \
|
|
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
|
|
|
|
/* func init flags */
|
|
#define FUNC_FLG_STATS 0x0001
|
|
#define FUNC_FLG_TPA 0x0002
|
|
#define FUNC_FLG_SPQ 0x0004
|
|
#define FUNC_FLG_LEADING 0x0008 /* PF only */
|
|
|
|
struct rxq_pause_params {
|
|
u16 bd_th_lo;
|
|
u16 bd_th_hi;
|
|
u16 rcq_th_lo;
|
|
u16 rcq_th_hi;
|
|
u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */
|
|
u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */
|
|
u16 pri_map;
|
|
};
|
|
|
|
struct bnx2x_rxq_init_params {
|
|
/* cxt*/
|
|
struct eth_context *cxt;
|
|
|
|
/* dma */
|
|
dma_addr_t dscr_map;
|
|
dma_addr_t sge_map;
|
|
dma_addr_t rcq_map;
|
|
dma_addr_t rcq_np_map;
|
|
|
|
u16 flags;
|
|
u16 drop_flags;
|
|
u16 mtu;
|
|
u16 buf_sz;
|
|
u16 fw_sb_id;
|
|
u16 cl_id;
|
|
u16 spcl_id;
|
|
u16 cl_qzone_id;
|
|
|
|
/* valid iff QUEUE_FLG_STATS */
|
|
u16 stat_id;
|
|
|
|
/* valid iff QUEUE_FLG_TPA */
|
|
u16 tpa_agg_sz;
|
|
u16 sge_buf_sz;
|
|
u16 max_sges_pkt;
|
|
|
|
/* valid iff QUEUE_FLG_CACHE_ALIGN */
|
|
u8 cache_line_log;
|
|
|
|
u8 sb_cq_index;
|
|
u32 cid;
|
|
|
|
/* desired interrupts per sec. valid iff QUEUE_FLG_HC */
|
|
u32 hc_rate;
|
|
};
|
|
|
|
struct bnx2x_txq_init_params {
|
|
/* cxt*/
|
|
struct eth_context *cxt;
|
|
|
|
/* dma */
|
|
dma_addr_t dscr_map;
|
|
|
|
u16 flags;
|
|
u16 fw_sb_id;
|
|
u8 sb_cq_index;
|
|
u8 cos; /* valid iff QUEUE_FLG_COS */
|
|
u16 stat_id; /* valid iff QUEUE_FLG_STATS */
|
|
u16 traffic_type;
|
|
u32 cid;
|
|
u16 hc_rate; /* desired interrupts per sec.*/
|
|
/* valid iff QUEUE_FLG_HC */
|
|
|
|
};
|
|
|
|
struct bnx2x_client_ramrod_params {
|
|
int *pstate;
|
|
int state;
|
|
u16 index;
|
|
u16 cl_id;
|
|
u32 cid;
|
|
u8 poll;
|
|
#define CLIENT_IS_FCOE 0x01
|
|
#define CLIENT_IS_LEADING_RSS 0x02
|
|
u8 flags;
|
|
};
|
|
|
|
struct bnx2x_client_init_params {
|
|
struct rxq_pause_params pause;
|
|
struct bnx2x_rxq_init_params rxq_params;
|
|
struct bnx2x_txq_init_params txq_params;
|
|
struct bnx2x_client_ramrod_params ramrod_params;
|
|
};
|
|
|
|
struct bnx2x_rss_params {
|
|
int mode;
|
|
u16 cap;
|
|
u16 result_mask;
|
|
};
|
|
|
|
struct bnx2x_func_init_params {
|
|
|
|
/* rss */
|
|
struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */
|
|
|
|
/* dma */
|
|
dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
|
|
dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
|
|
|
|
u16 func_flgs;
|
|
u16 func_id; /* abs fid */
|
|
u16 pf_id;
|
|
u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
|
|
};
|
|
|
|
#define for_each_eth_queue(bp, var) \
|
|
for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
|
|
|
|
#define for_each_nondefault_eth_queue(bp, var) \
|
|
for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
|
|
|
|
#define for_each_napi_queue(bp, var) \
|
|
for (var = 0; \
|
|
var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \
|
|
if (skip_queue(bp, var)) \
|
|
continue; \
|
|
else
|
|
|
|
#define for_each_queue(bp, var) \
|
|
for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
|
|
if (skip_queue(bp, var)) \
|
|
continue; \
|
|
else
|
|
|
|
#define for_each_rx_queue(bp, var) \
|
|
for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
|
|
if (skip_rx_queue(bp, var)) \
|
|
continue; \
|
|
else
|
|
|
|
#define for_each_tx_queue(bp, var) \
|
|
for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
|
|
if (skip_tx_queue(bp, var)) \
|
|
continue; \
|
|
else
|
|
|
|
#define for_each_nondefault_queue(bp, var) \
|
|
for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \
|
|
if (skip_queue(bp, var)) \
|
|
continue; \
|
|
else
|
|
|
|
/* skip rx queue
|
|
* if FCOE l2 support is disabled and this is the fcoe L2 queue
|
|
*/
|
|
#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
|
|
|
|
/* skip tx queue
|
|
* if FCOE l2 support is disabled and this is the fcoe L2 queue
|
|
*/
|
|
#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
|
|
|
|
#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
|
|
|
|
#define WAIT_RAMROD_POLL 0x01
|
|
#define WAIT_RAMROD_COMMON 0x02
|
|
|
|
void bnx2x_read_mf_cfg(struct bnx2x *bp);
|
|
|
|
/* dmae */
|
|
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
|
|
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
|
|
u32 len32);
|
|
void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
|
|
u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
|
|
u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
|
|
u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
|
|
bool with_comp, u8 comp_type);
|
|
|
|
int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
|
|
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
|
|
int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
|
|
u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
|
|
|
|
void bnx2x_calc_fc_adv(struct bnx2x *bp);
|
|
int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
|
|
u32 data_hi, u32 data_lo, int common);
|
|
|
|
/* Clears multicast and unicast list configuration in the chip. */
|
|
void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp);
|
|
void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp);
|
|
void bnx2x_invalidate_uc_list(struct bnx2x *bp);
|
|
|
|
void bnx2x_update_coalesce(struct bnx2x *bp);
|
|
int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
|
|
|
|
static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
|
|
int wait)
|
|
{
|
|
u32 val;
|
|
|
|
do {
|
|
val = REG_RD(bp, reg);
|
|
if (val == expected)
|
|
break;
|
|
ms -= wait;
|
|
msleep(wait);
|
|
|
|
} while (ms > 0);
|
|
|
|
return val;
|
|
}
|
|
|
|
#define BNX2X_ILT_ZALLOC(x, y, size) \
|
|
do { \
|
|
x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
|
|
if (x) \
|
|
memset(x, 0, size); \
|
|
} while (0)
|
|
|
|
#define BNX2X_ILT_FREE(x, y, size) \
|
|
do { \
|
|
if (x) { \
|
|
dma_free_coherent(&bp->pdev->dev, size, x, y); \
|
|
x = NULL; \
|
|
y = 0; \
|
|
} \
|
|
} while (0)
|
|
|
|
#define ILOG2(x) (ilog2((x)))
|
|
|
|
#define ILT_NUM_PAGE_ENTRIES (3072)
|
|
/* In 57710/11 we use whole table since we have 8 func
|
|
* In 57712 we have only 4 func, but use same size per func, then only half of
|
|
* the table in use
|
|
*/
|
|
#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
|
|
|
|
#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
|
|
/*
|
|
* the phys address is shifted right 12 bits and has an added
|
|
* 1=valid bit added to the 53rd bit
|
|
* then since this is a wide register(TM)
|
|
* we split it into two 32 bit writes
|
|
*/
|
|
#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
|
|
#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
|
|
|
|
/* load/unload mode */
|
|
#define LOAD_NORMAL 0
|
|
#define LOAD_OPEN 1
|
|
#define LOAD_DIAG 2
|
|
#define UNLOAD_NORMAL 0
|
|
#define UNLOAD_CLOSE 1
|
|
#define UNLOAD_RECOVERY 2
|
|
|
|
|
|
/* DMAE command defines */
|
|
#define DMAE_TIMEOUT -1
|
|
#define DMAE_PCI_ERROR -2 /* E2 and onward */
|
|
#define DMAE_NOT_RDY -3
|
|
#define DMAE_PCI_ERR_FLAG 0x80000000
|
|
|
|
#define DMAE_SRC_PCI 0
|
|
#define DMAE_SRC_GRC 1
|
|
|
|
#define DMAE_DST_NONE 0
|
|
#define DMAE_DST_PCI 1
|
|
#define DMAE_DST_GRC 2
|
|
|
|
#define DMAE_COMP_PCI 0
|
|
#define DMAE_COMP_GRC 1
|
|
|
|
/* E2 and onward - PCI error handling in the completion */
|
|
|
|
#define DMAE_COMP_REGULAR 0
|
|
#define DMAE_COM_SET_ERR 1
|
|
|
|
#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
|
|
DMAE_COMMAND_SRC_SHIFT)
|
|
#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
|
|
DMAE_COMMAND_SRC_SHIFT)
|
|
|
|
#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
|
|
DMAE_COMMAND_DST_SHIFT)
|
|
#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
|
|
DMAE_COMMAND_DST_SHIFT)
|
|
|
|
#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
|
|
DMAE_COMMAND_C_DST_SHIFT)
|
|
#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
|
|
DMAE_COMMAND_C_DST_SHIFT)
|
|
|
|
#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
|
|
|
|
#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
|
|
#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
|
|
#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
|
|
#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
|
|
|
|
#define DMAE_CMD_PORT_0 0
|
|
#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
|
|
|
|
#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
|
|
#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
|
|
#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
|
|
|
|
#define DMAE_SRC_PF 0
|
|
#define DMAE_SRC_VF 1
|
|
|
|
#define DMAE_DST_PF 0
|
|
#define DMAE_DST_VF 1
|
|
|
|
#define DMAE_C_SRC 0
|
|
#define DMAE_C_DST 1
|
|
|
|
#define DMAE_LEN32_RD_MAX 0x80
|
|
#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
|
|
|
|
#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
|
|
indicates eror */
|
|
|
|
#define MAX_DMAE_C_PER_PORT 8
|
|
#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
|
|
BP_E1HVN(bp))
|
|
#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
|
|
E1HVN_MAX)
|
|
|
|
/* PCIE link and speed */
|
|
#define PCICFG_LINK_WIDTH 0x1f00000
|
|
#define PCICFG_LINK_WIDTH_SHIFT 20
|
|
#define PCICFG_LINK_SPEED 0xf0000
|
|
#define PCICFG_LINK_SPEED_SHIFT 16
|
|
|
|
|
|
#define BNX2X_NUM_TESTS 7
|
|
|
|
#define BNX2X_PHY_LOOPBACK 0
|
|
#define BNX2X_MAC_LOOPBACK 1
|
|
#define BNX2X_PHY_LOOPBACK_FAILED 1
|
|
#define BNX2X_MAC_LOOPBACK_FAILED 2
|
|
#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
|
|
BNX2X_PHY_LOOPBACK_FAILED)
|
|
|
|
|
|
#define STROM_ASSERT_ARRAY_SIZE 50
|
|
|
|
|
|
/* must be used on a CID before placing it on a HW ring */
|
|
#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
|
|
(BP_E1HVN(bp) << 17) | (x))
|
|
|
|
#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
|
|
#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
|
|
|
|
|
|
#define BNX2X_BTR 4
|
|
#define MAX_SPQ_PENDING 8
|
|
|
|
/* CMNG constants, as derived from system spec calculations */
|
|
/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
|
|
#define DEF_MIN_RATE 100
|
|
/* resolution of the rate shaping timer - 400 usec */
|
|
#define RS_PERIODIC_TIMEOUT_USEC 400
|
|
/* number of bytes in single QM arbitration cycle -
|
|
* coefficient for calculating the fairness timer */
|
|
#define QM_ARB_BYTES 160000
|
|
/* resolution of Min algorithm 1:100 */
|
|
#define MIN_RES 100
|
|
/* how many bytes above threshold for the minimal credit of Min algorithm*/
|
|
#define MIN_ABOVE_THRESH 32768
|
|
/* Fairness algorithm integration time coefficient -
|
|
* for calculating the actual Tfair */
|
|
#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
|
|
/* Memory of fairness algorithm . 2 cycles */
|
|
#define FAIR_MEM 2
|
|
|
|
|
|
#define ATTN_NIG_FOR_FUNC (1L << 8)
|
|
#define ATTN_SW_TIMER_4_FUNC (1L << 9)
|
|
#define GPIO_2_FUNC (1L << 10)
|
|
#define GPIO_3_FUNC (1L << 11)
|
|
#define GPIO_4_FUNC (1L << 12)
|
|
#define ATTN_GENERAL_ATTN_1 (1L << 13)
|
|
#define ATTN_GENERAL_ATTN_2 (1L << 14)
|
|
#define ATTN_GENERAL_ATTN_3 (1L << 15)
|
|
#define ATTN_GENERAL_ATTN_4 (1L << 13)
|
|
#define ATTN_GENERAL_ATTN_5 (1L << 14)
|
|
#define ATTN_GENERAL_ATTN_6 (1L << 15)
|
|
|
|
#define ATTN_HARD_WIRED_MASK 0xff00
|
|
#define ATTENTION_ID 4
|
|
|
|
|
|
/* stuff added to make the code fit 80Col */
|
|
|
|
#define BNX2X_PMF_LINK_ASSERT \
|
|
GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
|
|
|
|
#define BNX2X_MC_ASSERT_BITS \
|
|
(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
|
|
GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
|
|
GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
|
|
GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
|
|
|
|
#define BNX2X_MCP_ASSERT \
|
|
GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
|
|
|
|
#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
|
|
#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
|
|
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
|
|
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
|
|
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
|
|
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
|
|
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
|
|
|
|
#define HW_INTERRUT_ASSERT_SET_0 \
|
|
(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
|
|
#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
|
|
AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
|
|
AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
|
|
AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
|
|
AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
|
|
#define HW_INTERRUT_ASSERT_SET_1 \
|
|
(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
|
|
AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
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AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
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AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
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AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
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AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
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#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
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AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
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AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
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AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
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#define HW_INTERRUT_ASSERT_SET_2 \
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(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
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AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
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AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
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AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
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AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
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#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
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AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
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|
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#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
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#define RSS_FLAGS(bp) \
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(TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
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TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
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TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
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TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
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(bp->multi_mode << \
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TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
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#define MULTI_MASK 0x7f
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|
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#define BNX2X_SP_DSB_INDEX \
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(&bp->def_status_blk->sp_sb.\
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index_values[HC_SP_INDEX_ETH_DEF_CONS])
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#define SET_FLAG(value, mask, flag) \
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do {\
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(value) &= ~(mask);\
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(value) |= ((flag) << (mask##_SHIFT));\
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} while (0)
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#define GET_FLAG(value, mask) \
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(((value) &= (mask)) >> (mask##_SHIFT))
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|
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#define GET_FIELD(value, fname) \
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(((value) & (fname##_MASK)) >> (fname##_SHIFT))
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|
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#define CAM_IS_INVALID(x) \
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|
(GET_FLAG(x.flags, \
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MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
|
|
(T_ETH_MAC_COMMAND_INVALIDATE))
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|
|
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/* Number of u32 elements in MC hash array */
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|
#define MC_HASH_SIZE 8
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|
#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
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TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
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|
|
|
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#ifndef PXP2_REG_PXP2_INT_STS
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|
#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
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|
#endif
|
|
|
|
#ifndef ETH_MAX_RX_CLIENTS_E2
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|
#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
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|
#endif
|
|
|
|
#define BNX2X_VPD_LEN 128
|
|
#define VENDOR_ID_LEN 4
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|
|
|
/* Congestion management fairness mode */
|
|
#define CMNG_FNS_NONE 0
|
|
#define CMNG_FNS_MINMAX 1
|
|
|
|
#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
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|
#define HC_SEG_ACCESS_ATTN 4
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|
#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
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|
|
|
#ifdef BNX2X_MAIN
|
|
#define BNX2X_EXTERN
|
|
#else
|
|
#define BNX2X_EXTERN extern
|
|
#endif
|
|
|
|
BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */
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|
|
|
extern void bnx2x_set_ethtool_ops(struct net_device *netdev);
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|
void bnx2x_push_indir_table(struct bnx2x *bp);
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|
|
|
#endif /* bnx2x.h */
|