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![Dmitry Kravkov](/assets/img/avatar_default.png)
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
416 lines
11 KiB
C
416 lines
11 KiB
C
/* bnx2x_init.h: Broadcom Everest network driver.
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* Structures and macroes needed during the initialization.
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*
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* Copyright (c) 2007-2011 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Modified by: Vladislav Zolotarov <vladz@broadcom.com>
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*/
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#ifndef BNX2X_INIT_H
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#define BNX2X_INIT_H
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/* RAM0 size in bytes */
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#define STORM_INTMEM_SIZE_E1 0x5800
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#define STORM_INTMEM_SIZE_E1H 0x10000
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#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
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STORM_INTMEM_SIZE_E1H) / 4)
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/* Init operation types and structures */
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/* Common for both E1 and E1H */
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#define OP_RD 0x1 /* read single register */
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#define OP_WR 0x2 /* write single register */
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#define OP_IW 0x3 /* write single register using mailbox */
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#define OP_SW 0x4 /* copy a string to the device */
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#define OP_SI 0x5 /* copy a string using mailbox */
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#define OP_ZR 0x6 /* clear memory */
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#define OP_ZP 0x7 /* unzip then copy with DMAE */
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#define OP_WR_64 0x8 /* write 64 bit pattern */
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#define OP_WB 0x9 /* copy a string using DMAE */
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/* FPGA and EMUL specific operations */
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#define OP_WR_EMUL 0xa /* write single register on Emulation */
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#define OP_WR_FPGA 0xb /* write single register on FPGA */
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#define OP_WR_ASIC 0xc /* write single register on ASIC */
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/* Init stages */
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/* Never reorder stages !!! */
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#define COMMON_STAGE 0
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#define PORT0_STAGE 1
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#define PORT1_STAGE 2
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#define FUNC0_STAGE 3
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#define FUNC1_STAGE 4
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#define FUNC2_STAGE 5
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#define FUNC3_STAGE 6
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#define FUNC4_STAGE 7
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#define FUNC5_STAGE 8
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#define FUNC6_STAGE 9
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#define FUNC7_STAGE 10
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#define STAGE_IDX_MAX 11
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#define STAGE_START 0
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#define STAGE_END 1
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/* Indices of blocks */
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#define PRS_BLOCK 0
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#define SRCH_BLOCK 1
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#define TSDM_BLOCK 2
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#define TCM_BLOCK 3
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#define BRB1_BLOCK 4
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#define TSEM_BLOCK 5
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#define PXPCS_BLOCK 6
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#define EMAC0_BLOCK 7
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#define EMAC1_BLOCK 8
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#define DBU_BLOCK 9
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#define MISC_BLOCK 10
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#define DBG_BLOCK 11
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#define NIG_BLOCK 12
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#define MCP_BLOCK 13
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#define UPB_BLOCK 14
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#define CSDM_BLOCK 15
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#define USDM_BLOCK 16
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#define CCM_BLOCK 17
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#define UCM_BLOCK 18
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#define USEM_BLOCK 19
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#define CSEM_BLOCK 20
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#define XPB_BLOCK 21
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#define DQ_BLOCK 22
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#define TIMERS_BLOCK 23
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#define XSDM_BLOCK 24
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#define QM_BLOCK 25
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#define PBF_BLOCK 26
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#define XCM_BLOCK 27
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#define XSEM_BLOCK 28
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#define CDU_BLOCK 29
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#define DMAE_BLOCK 30
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#define PXP_BLOCK 31
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#define CFC_BLOCK 32
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#define HC_BLOCK 33
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#define PXP2_BLOCK 34
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#define MISC_AEU_BLOCK 35
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#define PGLUE_B_BLOCK 36
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#define IGU_BLOCK 37
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#define ATC_BLOCK 38
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#define QM_4PORT_BLOCK 39
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#define XSEM_4PORT_BLOCK 40
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/* Returns the index of start or end of a specific block stage in ops array*/
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#define BLOCK_OPS_IDX(block, stage, end) \
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(2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
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struct raw_op {
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u32 op:8;
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u32 offset:24;
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u32 raw_data;
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};
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struct op_read {
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u32 op:8;
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u32 offset:24;
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u32 pad;
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};
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struct op_write {
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u32 op:8;
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u32 offset:24;
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u32 val;
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};
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struct op_string_write {
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u32 op:8;
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u32 offset:24;
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#ifdef __LITTLE_ENDIAN
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u16 data_off;
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u16 data_len;
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#else /* __BIG_ENDIAN */
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u16 data_len;
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u16 data_off;
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#endif
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};
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struct op_zero {
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u32 op:8;
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u32 offset:24;
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u32 len;
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};
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union init_op {
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struct op_read read;
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struct op_write write;
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struct op_string_write str_wr;
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struct op_zero zero;
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struct raw_op raw;
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};
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#define INITOP_SET 0 /* set the HW directly */
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#define INITOP_CLEAR 1 /* clear the HW directly */
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#define INITOP_INIT 2 /* set the init-value array */
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/****************************************************************************
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* ILT management
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****************************************************************************/
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struct ilt_line {
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dma_addr_t page_mapping;
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void *page;
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u32 size;
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};
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struct ilt_client_info {
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u32 page_size;
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u16 start;
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u16 end;
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u16 client_num;
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u16 flags;
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#define ILT_CLIENT_SKIP_INIT 0x1
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#define ILT_CLIENT_SKIP_MEM 0x2
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};
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struct bnx2x_ilt {
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u32 start_line;
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struct ilt_line *lines;
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struct ilt_client_info clients[4];
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#define ILT_CLIENT_CDU 0
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#define ILT_CLIENT_QM 1
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#define ILT_CLIENT_SRC 2
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#define ILT_CLIENT_TM 3
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};
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/****************************************************************************
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* SRC configuration
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****************************************************************************/
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struct src_ent {
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u8 opaque[56];
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u64 next;
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};
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/****************************************************************************
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* Parity configuration
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****************************************************************************/
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#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \
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{ \
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block##_REG_##block##_PRTY_MASK, \
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block##_REG_##block##_PRTY_STS_CLR, \
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en_mask, {m1, m1h, m2}, #block \
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}
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#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \
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{ \
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block##_REG_##block##_PRTY_MASK_0, \
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block##_REG_##block##_PRTY_STS_CLR_0, \
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en_mask, {m1, m1h, m2}, #block"_0" \
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}
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#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \
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{ \
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block##_REG_##block##_PRTY_MASK_1, \
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block##_REG_##block##_PRTY_STS_CLR_1, \
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en_mask, {m1, m1h, m2}, #block"_1" \
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}
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static const struct {
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u32 mask_addr;
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u32 sts_clr_addr;
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u32 en_mask; /* Mask to enable parity attentions */
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struct {
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u32 e1; /* 57710 */
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u32 e1h; /* 57711 */
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u32 e2; /* 57712 */
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} reg_mask; /* Register mask (all valid bits) */
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char name[7]; /* Block's longest name is 6 characters long
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* (name + suffix)
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*/
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} bnx2x_blocks_parity_data[] = {
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/* bit 19 masked */
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/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
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/* bit 5,18,20-31 */
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/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
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/* bit 5 */
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/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
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/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
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/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
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/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
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* want to handle "system kill" flow at the moment.
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*/
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BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
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BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
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BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
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BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
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BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
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{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0,
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{0xf, 0xf, 0xf}, "UPB"},
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{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
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{0xf, 0xf, 0xf}, "XPB"},
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BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
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BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
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BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
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BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),
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};
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/* [28] MCP Latched rom_parity
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* [29] MCP Latched ump_rx_parity
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* [30] MCP Latched ump_tx_parity
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* [31] MCP Latched scpad_parity
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*/
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#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
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(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
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/* Below registers control the MCP parity attention output. When
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* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
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* enabled, when cleared - disabled.
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*/
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static const u32 mcp_attn_ctl_regs[] = {
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MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_0,
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MISC_REG_AEU_ENABLE4_PXP_0,
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MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_1,
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MISC_REG_AEU_ENABLE4_PXP_1
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};
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static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
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{
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int i;
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u32 reg_val;
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for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
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reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
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if (enable)
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reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
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else
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reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
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REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
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}
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}
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static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
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{
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if (CHIP_IS_E1(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e1;
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else if (CHIP_IS_E1H(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
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else
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return bnx2x_blocks_parity_data[idx].reg_mask.e2;
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}
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static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
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if (dis_mask) {
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REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
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dis_mask);
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DP(NETIF_MSG_HW, "Setting parity mask "
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"for %s to\t\t0x%x\n",
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bnx2x_blocks_parity_data[i].name, dis_mask);
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}
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}
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/* Disable MCP parity attentions */
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bnx2x_set_mcp_parity(bp, false);
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}
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/**
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* Clear the parity error status registers.
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*/
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static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
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{
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int i;
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u32 reg_val, mcp_aeu_bits =
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
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/* Clear SEM_FAST parities */
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REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
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if (reg_mask) {
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reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
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sts_clr_addr);
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if (reg_val & reg_mask)
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DP(NETIF_MSG_HW,
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"Parity errors in %s: 0x%x\n",
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bnx2x_blocks_parity_data[i].name,
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reg_val & reg_mask);
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}
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}
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/* Check if there were parity attentions in MCP */
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reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
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if (reg_val & mcp_aeu_bits)
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DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
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reg_val & mcp_aeu_bits);
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/* Clear parity attentions in MCP:
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* [7] clears Latched rom_parity
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* [8] clears Latched ump_rx_parity
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* [9] clears Latched ump_tx_parity
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* [10] clears Latched scpad_parity (both ports)
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*/
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REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
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}
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static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
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if (reg_mask)
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REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
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bnx2x_blocks_parity_data[i].en_mask & reg_mask);
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}
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/* Enable MCP parity attentions */
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bnx2x_set_mcp_parity(bp, true);
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}
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#endif /* BNX2X_INIT_H */
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