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![Russell King](/assets/img/avatar_default.png)
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
212 lines
5.3 KiB
C
212 lines
5.3 KiB
C
/*
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* Generic library functions for the MSF (Media and Switch Fabric) unit
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* found on the Intel IXP2400 network processor.
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*
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* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
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* Dedicated to Marija Kulikova.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as
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* published by the Free Software Foundation; either version 2.1 of the
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* License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <mach/hardware.h>
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#include <mach/ixp2000-regs.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include "ixp2400-msf.h"
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/*
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* This is the Intel recommended PLL init procedure as described on
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* page 340 of the IXP2400/IXP2800 Programmer's Reference Manual.
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*/
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static void ixp2400_pll_init(struct ixp2400_msf_parameters *mp)
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{
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int rx_dual_clock;
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int tx_dual_clock;
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u32 value;
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/*
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* If the RX mode is not 1x32, we have to enable both RX PLLs
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* (#0 and #1.) The same thing for the TX direction.
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*/
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rx_dual_clock = !!(mp->rx_mode & IXP2400_RX_MODE_WIDTH_MASK);
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tx_dual_clock = !!(mp->tx_mode & IXP2400_TX_MODE_WIDTH_MASK);
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/*
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* Read initial value.
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*/
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value = ixp2000_reg_read(IXP2000_MSF_CLK_CNTRL);
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/*
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* Put PLLs in powerdown and bypass mode.
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*/
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value |= 0x0000f0f0;
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ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
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/*
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* Set single or dual clock mode bits.
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*/
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value &= ~0x03000000;
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value |= (rx_dual_clock << 24) | (tx_dual_clock << 25);
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/*
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* Set multipliers.
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*/
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value &= ~0x00ff0000;
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value |= mp->rxclk01_multiplier << 16;
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value |= mp->rxclk23_multiplier << 18;
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value |= mp->txclk01_multiplier << 20;
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value |= mp->txclk23_multiplier << 22;
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/*
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* And write value.
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*/
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ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
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/*
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* Disable PLL bypass mode.
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*/
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value &= ~(0x00005000 | rx_dual_clock << 13 | tx_dual_clock << 15);
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ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
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/*
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* Turn on PLLs.
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*/
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value &= ~(0x00000050 | rx_dual_clock << 5 | tx_dual_clock << 7);
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ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
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/*
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* Wait for PLLs to lock. There are lock status bits, but IXP2400
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* erratum #65 says that these lock bits should not be relied upon
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* as they might not accurately reflect the true state of the PLLs.
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*/
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udelay(100);
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}
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/*
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* Needed according to p480 of Programmer's Reference Manual.
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*/
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static void ixp2400_msf_free_rbuf_entries(struct ixp2400_msf_parameters *mp)
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{
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int size_bits;
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int i;
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/*
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* Work around IXP2400 erratum #69 (silent RBUF-to-DRAM transfer
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* corruption) in the Intel-recommended way: do not add the RBUF
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* elements susceptible to corruption to the freelist.
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*/
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size_bits = mp->rx_mode & IXP2400_RX_MODE_RBUF_SIZE_MASK;
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if (size_bits == IXP2400_RX_MODE_RBUF_SIZE_64) {
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for (i = 1; i < 128; i++) {
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if (i == 9 || i == 18 || i == 27)
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continue;
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ixp2000_reg_write(IXP2000_MSF_RBUF_ELEMENT_DONE, i);
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}
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} else if (size_bits == IXP2400_RX_MODE_RBUF_SIZE_128) {
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for (i = 1; i < 64; i++) {
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if (i == 4 || i == 9 || i == 13)
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continue;
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ixp2000_reg_write(IXP2000_MSF_RBUF_ELEMENT_DONE, i);
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}
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} else if (size_bits == IXP2400_RX_MODE_RBUF_SIZE_256) {
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for (i = 1; i < 32; i++) {
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if (i == 2 || i == 4 || i == 6)
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continue;
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ixp2000_reg_write(IXP2000_MSF_RBUF_ELEMENT_DONE, i);
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}
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}
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}
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static u32 ixp2400_msf_valid_channels(u32 reg)
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{
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u32 channels;
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channels = 0;
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switch (reg & IXP2400_RX_MODE_WIDTH_MASK) {
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case IXP2400_RX_MODE_1x32:
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channels = 0x1;
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if (reg & IXP2400_RX_MODE_MPHY &&
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!(reg & IXP2400_RX_MODE_MPHY_32))
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channels = 0xf;
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break;
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case IXP2400_RX_MODE_2x16:
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channels = 0x5;
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break;
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case IXP2400_RX_MODE_4x8:
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channels = 0xf;
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break;
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case IXP2400_RX_MODE_1x16_2x8:
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channels = 0xd;
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break;
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}
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return channels;
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}
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static void ixp2400_msf_enable_rx(struct ixp2400_msf_parameters *mp)
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{
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u32 value;
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value = ixp2000_reg_read(IXP2000_MSF_RX_CONTROL) & 0x0fffffff;
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value |= ixp2400_msf_valid_channels(mp->rx_mode) << 28;
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ixp2000_reg_write(IXP2000_MSF_RX_CONTROL, value);
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}
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static void ixp2400_msf_enable_tx(struct ixp2400_msf_parameters *mp)
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{
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u32 value;
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value = ixp2000_reg_read(IXP2000_MSF_TX_CONTROL) & 0x0fffffff;
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value |= ixp2400_msf_valid_channels(mp->tx_mode) << 28;
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ixp2000_reg_write(IXP2000_MSF_TX_CONTROL, value);
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}
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void ixp2400_msf_init(struct ixp2400_msf_parameters *mp)
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{
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u32 value;
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int i;
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/*
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* Init the RX/TX PLLs based on the passed parameter block.
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*/
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ixp2400_pll_init(mp);
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/*
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* Reset MSF. Bit 7 in IXP_RESET_0 resets the MSF.
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*/
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value = ixp2000_reg_read(IXP2000_RESET0);
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ixp2000_reg_write(IXP2000_RESET0, value | 0x80);
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ixp2000_reg_write(IXP2000_RESET0, value & ~0x80);
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/*
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* Initialise the RX section.
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*/
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ixp2000_reg_write(IXP2000_MSF_RX_MPHY_POLL_LIMIT, mp->rx_poll_ports - 1);
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ixp2000_reg_write(IXP2000_MSF_RX_CONTROL, mp->rx_mode);
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for (i = 0; i < 4; i++) {
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ixp2000_reg_write(IXP2000_MSF_RX_UP_CONTROL_0 + i,
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mp->rx_channel_mode[i]);
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}
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ixp2400_msf_free_rbuf_entries(mp);
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ixp2400_msf_enable_rx(mp);
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/*
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* Initialise the TX section.
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*/
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ixp2000_reg_write(IXP2000_MSF_TX_MPHY_POLL_LIMIT, mp->tx_poll_ports - 1);
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ixp2000_reg_write(IXP2000_MSF_TX_CONTROL, mp->tx_mode);
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for (i = 0; i < 4; i++) {
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ixp2000_reg_write(IXP2000_MSF_TX_UP_CONTROL_0 + i,
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mp->tx_channel_mode[i]);
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}
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ixp2400_msf_enable_tx(mp);
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}
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