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![Jan Andersson](/assets/img/avatar_default.png)
The two first HC capability registers (CAPLENGTH and HCIVERSION) are defined as one 8-bit and one 16-bit register. Most HC implementations have selected to treat these registers as part of a 32-bit register, giving the same layout for both big and small endian systems. This patch adds a new quirk, big_endian_capbase, to support controllers with big endian register interfaces that treat HCIVERSION and CAPLENGTH as individual registers. Signed-off-by: Jan Andersson <jan@gaisler.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
787 lines
20 KiB
C
787 lines
20 KiB
C
/*
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* EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2009 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/tegra_usb.h>
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#include <linux/irq.h>
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#include <linux/usb/otg.h>
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#include <mach/usb_phy.h>
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#define TEGRA_USB_DMA_ALIGN 32
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struct tegra_ehci_hcd {
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struct ehci_hcd *ehci;
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struct tegra_usb_phy *phy;
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struct clk *clk;
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struct clk *emc_clk;
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struct otg_transceiver *transceiver;
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int host_resumed;
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int bus_suspended;
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int port_resuming;
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int power_down_on_bus_suspend;
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enum tegra_usb_phy_port_speed port_speed;
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};
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static void tegra_ehci_power_up(struct usb_hcd *hcd)
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{
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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clk_enable(tegra->emc_clk);
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clk_enable(tegra->clk);
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tegra_usb_phy_power_on(tegra->phy);
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tegra->host_resumed = 1;
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}
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static void tegra_ehci_power_down(struct usb_hcd *hcd)
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{
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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tegra->host_resumed = 0;
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tegra_usb_phy_power_off(tegra->phy);
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clk_disable(tegra->clk);
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clk_disable(tegra->emc_clk);
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}
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static int tegra_ehci_internal_port_reset(
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struct ehci_hcd *ehci,
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u32 __iomem *portsc_reg
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)
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{
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u32 temp;
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unsigned long flags;
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int retval = 0;
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int i, tries;
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u32 saved_usbintr;
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spin_lock_irqsave(&ehci->lock, flags);
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saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
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/* disable USB interrupt */
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ehci_writel(ehci, 0, &ehci->regs->intr_enable);
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spin_unlock_irqrestore(&ehci->lock, flags);
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/*
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* Here we have to do Port Reset at most twice for
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* Port Enable bit to be set.
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*/
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for (i = 0; i < 2; i++) {
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temp = ehci_readl(ehci, portsc_reg);
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temp |= PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(10);
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temp &= ~PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(1);
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tries = 100;
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do {
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mdelay(1);
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/*
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* Up to this point, Port Enable bit is
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* expected to be set after 2 ms waiting.
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* USB1 usually takes extra 45 ms, for safety,
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* we take 100 ms as timeout.
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*/
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temp = ehci_readl(ehci, portsc_reg);
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} while (!(temp & PORT_PE) && tries--);
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if (temp & PORT_PE)
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break;
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}
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if (i == 2)
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retval = -ETIMEDOUT;
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/*
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* Clear Connect Status Change bit if it's set.
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* We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
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*/
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if (temp & PORT_CSC)
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ehci_writel(ehci, PORT_CSC, portsc_reg);
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/*
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* Write to clear any interrupt status bits that might be set
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* during port reset.
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*/
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temp = ehci_readl(ehci, &ehci->regs->status);
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ehci_writel(ehci, temp, &ehci->regs->status);
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/* restore original interrupt enable bits */
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ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
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return retval;
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}
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static int tegra_ehci_hub_control(
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struct usb_hcd *hcd,
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u16 typeReq,
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u16 wValue,
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u16 wIndex,
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char *buf,
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u16 wLength
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)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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u32 __iomem *status_reg;
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u32 temp;
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unsigned long flags;
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int retval = 0;
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status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
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spin_lock_irqsave(&ehci->lock, flags);
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/*
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* In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
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* that are write on clear, by writing back the register read value, so
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* USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
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*/
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if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
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temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
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ehci_writel(ehci, temp & ~PORT_PE, status_reg);
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goto done;
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}
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else if (typeReq == GetPortStatus) {
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temp = ehci_readl(ehci, status_reg);
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if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
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/* Resume completed, re-enable disconnect detection */
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tegra->port_resuming = 0;
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tegra_usb_phy_postresume(tegra->phy);
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}
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}
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else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
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temp = ehci_readl(ehci, status_reg);
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if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
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retval = -EPIPE;
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goto done;
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}
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temp &= ~PORT_WKCONN_E;
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temp |= PORT_WKDISC_E | PORT_WKOC_E;
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ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
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/*
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* If a transaction is in progress, there may be a delay in
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* suspending the port. Poll until the port is suspended.
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*/
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if (handshake(ehci, status_reg, PORT_SUSPEND,
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PORT_SUSPEND, 5000))
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pr_err("%s: timeout waiting for SUSPEND\n", __func__);
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set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
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goto done;
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}
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/* For USB1 port we need to issue Port Reset twice internally */
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if (tegra->phy->instance == 0 &&
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(typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
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spin_unlock_irqrestore(&ehci->lock, flags);
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return tegra_ehci_internal_port_reset(ehci, status_reg);
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}
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/*
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* Tegra host controller will time the resume operation to clear the bit
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* when the port control state switches to HS or FS Idle. This behavior
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* is different from EHCI where the host controller driver is required
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* to set this bit to a zero after the resume duration is timed in the
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* driver.
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*/
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else if (typeReq == ClearPortFeature &&
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wValue == USB_PORT_FEAT_SUSPEND) {
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temp = ehci_readl(ehci, status_reg);
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if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
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retval = -EPIPE;
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goto done;
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}
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if (!(temp & PORT_SUSPEND))
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goto done;
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/* Disable disconnect detection during port resume */
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tegra_usb_phy_preresume(tegra->phy);
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ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
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temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
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/* start resume signalling */
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ehci_writel(ehci, temp | PORT_RESUME, status_reg);
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spin_unlock_irqrestore(&ehci->lock, flags);
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msleep(20);
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spin_lock_irqsave(&ehci->lock, flags);
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/* Poll until the controller clears RESUME and SUSPEND */
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if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
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pr_err("%s: timeout waiting for RESUME\n", __func__);
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if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
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pr_err("%s: timeout waiting for SUSPEND\n", __func__);
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ehci->reset_done[wIndex-1] = 0;
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tegra->port_resuming = 1;
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goto done;
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}
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spin_unlock_irqrestore(&ehci->lock, flags);
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/* Handle the hub control events here */
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return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
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done:
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spin_unlock_irqrestore(&ehci->lock, flags);
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return retval;
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}
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static void tegra_ehci_restart(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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ehci_reset(ehci);
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/* setup the frame list and Async q heads */
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ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
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ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
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/* setup the command register and set the controller in RUN mode */
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ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
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ehci->command |= CMD_RUN;
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ehci_writel(ehci, ehci->command, &ehci->regs->command);
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down_write(&ehci_cf_port_reset_rwsem);
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ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
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/* flush posted writes */
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ehci_readl(ehci, &ehci->regs->command);
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up_write(&ehci_cf_port_reset_rwsem);
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}
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static int tegra_usb_suspend(struct usb_hcd *hcd)
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{
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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struct ehci_regs __iomem *hw = tegra->ehci->regs;
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unsigned long flags;
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spin_lock_irqsave(&tegra->ehci->lock, flags);
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tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
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ehci_halt(tegra->ehci);
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clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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spin_unlock_irqrestore(&tegra->ehci->lock, flags);
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tegra_ehci_power_down(hcd);
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return 0;
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}
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static int tegra_usb_resume(struct usb_hcd *hcd)
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{
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct ehci_regs __iomem *hw = ehci->regs;
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unsigned long val;
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set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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tegra_ehci_power_up(hcd);
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if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
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/* Wait for the phy to detect new devices
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* before we restart the controller */
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msleep(10);
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goto restart;
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}
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/* Force the phy to keep data lines in suspend state */
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tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
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/* Enable host mode */
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tdi_reset(ehci);
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/* Enable Port Power */
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val = readl(&hw->port_status[0]);
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val |= PORT_POWER;
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writel(val, &hw->port_status[0]);
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udelay(10);
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/* Check if the phy resume from LP0. When the phy resume from LP0
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* USB register will be reset. */
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if (!readl(&hw->async_next)) {
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/* Program the field PTC based on the saved speed mode */
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val = readl(&hw->port_status[0]);
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val &= ~PORT_TEST(~0);
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if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
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val |= PORT_TEST_FORCE;
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else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
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val |= PORT_TEST(6);
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else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
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val |= PORT_TEST(7);
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writel(val, &hw->port_status[0]);
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udelay(10);
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/* Disable test mode by setting PTC field to NORMAL_OP */
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val = readl(&hw->port_status[0]);
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val &= ~PORT_TEST(~0);
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writel(val, &hw->port_status[0]);
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udelay(10);
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}
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/* Poll until CCS is enabled */
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if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
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PORT_CONNECT, 2000)) {
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pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
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goto restart;
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}
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/* Poll until PE is enabled */
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if (handshake(ehci, &hw->port_status[0], PORT_PE,
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PORT_PE, 2000)) {
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pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
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goto restart;
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}
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/* Clear the PCI status, to avoid an interrupt taken upon resume */
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val = readl(&hw->status);
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val |= STS_PCD;
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writel(val, &hw->status);
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/* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
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val = readl(&hw->port_status[0]);
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if ((val & PORT_POWER) && (val & PORT_PE)) {
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val |= PORT_SUSPEND;
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writel(val, &hw->port_status[0]);
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/* Wait until port suspend completes */
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if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
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PORT_SUSPEND, 1000)) {
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pr_err("%s: timeout waiting for PORT_SUSPEND\n",
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__func__);
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goto restart;
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}
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}
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tegra_ehci_phy_restore_end(tegra->phy);
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return 0;
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restart:
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if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
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tegra_ehci_phy_restore_end(tegra->phy);
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tegra_ehci_restart(hcd);
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return 0;
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}
|
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|
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static void tegra_ehci_shutdown(struct usb_hcd *hcd)
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{
|
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
|
|
|
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/* ehci_shutdown touches the USB controller registers, make sure
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* controller has clocks to it */
|
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if (!tegra->host_resumed)
|
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tegra_ehci_power_up(hcd);
|
|
|
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ehci_shutdown(hcd);
|
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}
|
|
|
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static int tegra_ehci_setup(struct usb_hcd *hcd)
|
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{
|
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
|
int retval;
|
|
|
|
/* EHCI registers start at offset 0x100 */
|
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ehci->caps = hcd->regs + 0x100;
|
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ehci->regs = hcd->regs + 0x100 +
|
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HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
|
|
|
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dbg_hcs_params(ehci, "reset");
|
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dbg_hcc_params(ehci, "reset");
|
|
|
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/* cache this readonly data; minimize chip reads */
|
|
ehci->hcs_params = readl(&ehci->caps->hcs_params);
|
|
|
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/* switch to host mode */
|
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hcd->has_tt = 1;
|
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ehci_reset(ehci);
|
|
|
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retval = ehci_halt(ehci);
|
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if (retval)
|
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return retval;
|
|
|
|
/* data structure init */
|
|
retval = ehci_init(hcd);
|
|
if (retval)
|
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return retval;
|
|
|
|
ehci->sbrn = 0x20;
|
|
|
|
ehci_port_power(ehci, 1);
|
|
return retval;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
|
|
int error_status = 0;
|
|
|
|
error_status = ehci_bus_suspend(hcd);
|
|
if (!error_status && tegra->power_down_on_bus_suspend) {
|
|
tegra_usb_suspend(hcd);
|
|
tegra->bus_suspended = 1;
|
|
}
|
|
|
|
return error_status;
|
|
}
|
|
|
|
static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
|
|
|
|
if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
|
|
tegra_usb_resume(hcd);
|
|
tegra->bus_suspended = 0;
|
|
}
|
|
|
|
tegra_usb_phy_preresume(tegra->phy);
|
|
tegra->port_resuming = 1;
|
|
return ehci_bus_resume(hcd);
|
|
}
|
|
#endif
|
|
|
|
struct temp_buffer {
|
|
void *kmalloc_ptr;
|
|
void *old_xfer_buffer;
|
|
u8 data[0];
|
|
};
|
|
|
|
static void free_temp_buffer(struct urb *urb)
|
|
{
|
|
enum dma_data_direction dir;
|
|
struct temp_buffer *temp;
|
|
|
|
if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
|
|
return;
|
|
|
|
dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
|
|
|
|
temp = container_of(urb->transfer_buffer, struct temp_buffer,
|
|
data);
|
|
|
|
if (dir == DMA_FROM_DEVICE)
|
|
memcpy(temp->old_xfer_buffer, temp->data,
|
|
urb->transfer_buffer_length);
|
|
urb->transfer_buffer = temp->old_xfer_buffer;
|
|
kfree(temp->kmalloc_ptr);
|
|
|
|
urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
|
|
}
|
|
|
|
static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
|
|
{
|
|
enum dma_data_direction dir;
|
|
struct temp_buffer *temp, *kmalloc_ptr;
|
|
size_t kmalloc_size;
|
|
|
|
if (urb->num_sgs || urb->sg ||
|
|
urb->transfer_buffer_length == 0 ||
|
|
!((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
|
|
return 0;
|
|
|
|
dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
|
|
|
|
/* Allocate a buffer with enough padding for alignment */
|
|
kmalloc_size = urb->transfer_buffer_length +
|
|
sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
|
|
|
|
kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
|
|
if (!kmalloc_ptr)
|
|
return -ENOMEM;
|
|
|
|
/* Position our struct temp_buffer such that data is aligned */
|
|
temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
|
|
|
|
temp->kmalloc_ptr = kmalloc_ptr;
|
|
temp->old_xfer_buffer = urb->transfer_buffer;
|
|
if (dir == DMA_TO_DEVICE)
|
|
memcpy(temp->data, urb->transfer_buffer,
|
|
urb->transfer_buffer_length);
|
|
urb->transfer_buffer = temp->data;
|
|
|
|
urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
|
|
gfp_t mem_flags)
|
|
{
|
|
int ret;
|
|
|
|
ret = alloc_temp_buffer(urb, mem_flags);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
|
|
if (ret)
|
|
free_temp_buffer(urb);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
|
|
{
|
|
usb_hcd_unmap_urb_for_dma(hcd, urb);
|
|
free_temp_buffer(urb);
|
|
}
|
|
|
|
static const struct hc_driver tegra_ehci_hc_driver = {
|
|
.description = hcd_name,
|
|
.product_desc = "Tegra EHCI Host Controller",
|
|
.hcd_priv_size = sizeof(struct ehci_hcd),
|
|
|
|
.flags = HCD_USB2 | HCD_MEMORY,
|
|
|
|
.reset = tegra_ehci_setup,
|
|
.irq = ehci_irq,
|
|
|
|
.start = ehci_run,
|
|
.stop = ehci_stop,
|
|
.shutdown = tegra_ehci_shutdown,
|
|
.urb_enqueue = ehci_urb_enqueue,
|
|
.urb_dequeue = ehci_urb_dequeue,
|
|
.map_urb_for_dma = tegra_ehci_map_urb_for_dma,
|
|
.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
|
|
.endpoint_disable = ehci_endpoint_disable,
|
|
.endpoint_reset = ehci_endpoint_reset,
|
|
.get_frame_number = ehci_get_frame,
|
|
.hub_status_data = ehci_hub_status_data,
|
|
.hub_control = tegra_ehci_hub_control,
|
|
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
|
|
#ifdef CONFIG_PM
|
|
.bus_suspend = tegra_ehci_bus_suspend,
|
|
.bus_resume = tegra_ehci_bus_resume,
|
|
#endif
|
|
.relinquish_port = ehci_relinquish_port,
|
|
.port_handed_over = ehci_port_handed_over,
|
|
};
|
|
|
|
static int tegra_ehci_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct usb_hcd *hcd;
|
|
struct tegra_ehci_hcd *tegra;
|
|
struct tegra_ehci_platform_data *pdata;
|
|
int err = 0;
|
|
int irq;
|
|
int instance = pdev->id;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "Platform data missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
|
|
if (!tegra)
|
|
return -ENOMEM;
|
|
|
|
hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
|
|
dev_name(&pdev->dev));
|
|
if (!hcd) {
|
|
dev_err(&pdev->dev, "Unable to create HCD\n");
|
|
err = -ENOMEM;
|
|
goto fail_hcd;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, tegra);
|
|
|
|
tegra->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(tegra->clk)) {
|
|
dev_err(&pdev->dev, "Can't get ehci clock\n");
|
|
err = PTR_ERR(tegra->clk);
|
|
goto fail_clk;
|
|
}
|
|
|
|
err = clk_enable(tegra->clk);
|
|
if (err)
|
|
goto fail_clken;
|
|
|
|
tegra->emc_clk = clk_get(&pdev->dev, "emc");
|
|
if (IS_ERR(tegra->emc_clk)) {
|
|
dev_err(&pdev->dev, "Can't get emc clock\n");
|
|
err = PTR_ERR(tegra->emc_clk);
|
|
goto fail_emc_clk;
|
|
}
|
|
|
|
clk_enable(tegra->emc_clk);
|
|
clk_set_rate(tegra->emc_clk, 400000000);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "Failed to get I/O memory\n");
|
|
err = -ENXIO;
|
|
goto fail_io;
|
|
}
|
|
hcd->rsrc_start = res->start;
|
|
hcd->rsrc_len = resource_size(res);
|
|
hcd->regs = ioremap(res->start, resource_size(res));
|
|
if (!hcd->regs) {
|
|
dev_err(&pdev->dev, "Failed to remap I/O memory\n");
|
|
err = -ENOMEM;
|
|
goto fail_io;
|
|
}
|
|
|
|
tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
|
|
TEGRA_USB_PHY_MODE_HOST);
|
|
if (IS_ERR(tegra->phy)) {
|
|
dev_err(&pdev->dev, "Failed to open USB phy\n");
|
|
err = -ENXIO;
|
|
goto fail_phy;
|
|
}
|
|
|
|
err = tegra_usb_phy_power_on(tegra->phy);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to power on the phy\n");
|
|
goto fail;
|
|
}
|
|
|
|
tegra->host_resumed = 1;
|
|
tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
|
|
tegra->ehci = hcd_to_ehci(hcd);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (!irq) {
|
|
dev_err(&pdev->dev, "Failed to get IRQ\n");
|
|
err = -ENODEV;
|
|
goto fail;
|
|
}
|
|
set_irq_flags(irq, IRQF_VALID);
|
|
|
|
#ifdef CONFIG_USB_OTG_UTILS
|
|
if (pdata->operating_mode == TEGRA_USB_OTG) {
|
|
tegra->transceiver = otg_get_transceiver();
|
|
if (tegra->transceiver)
|
|
otg_set_host(tegra->transceiver, &hcd->self);
|
|
}
|
|
#endif
|
|
|
|
err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to add USB HCD\n");
|
|
goto fail;
|
|
}
|
|
|
|
return err;
|
|
|
|
fail:
|
|
#ifdef CONFIG_USB_OTG_UTILS
|
|
if (tegra->transceiver) {
|
|
otg_set_host(tegra->transceiver, NULL);
|
|
otg_put_transceiver(tegra->transceiver);
|
|
}
|
|
#endif
|
|
tegra_usb_phy_close(tegra->phy);
|
|
fail_phy:
|
|
iounmap(hcd->regs);
|
|
fail_io:
|
|
clk_disable(tegra->emc_clk);
|
|
clk_put(tegra->emc_clk);
|
|
fail_emc_clk:
|
|
clk_disable(tegra->clk);
|
|
fail_clken:
|
|
clk_put(tegra->clk);
|
|
fail_clk:
|
|
usb_put_hcd(hcd);
|
|
fail_hcd:
|
|
kfree(tegra);
|
|
return err;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int tegra_ehci_resume(struct platform_device *pdev)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
|
|
struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
|
|
|
|
if (tegra->bus_suspended)
|
|
return 0;
|
|
|
|
return tegra_usb_resume(hcd);
|
|
}
|
|
|
|
static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
|
|
struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
|
|
|
|
if (tegra->bus_suspended)
|
|
return 0;
|
|
|
|
if (time_before(jiffies, tegra->ehci->next_statechange))
|
|
msleep(10);
|
|
|
|
return tegra_usb_suspend(hcd);
|
|
}
|
|
#endif
|
|
|
|
static int tegra_ehci_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
|
|
struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
|
|
|
|
if (tegra == NULL || hcd == NULL)
|
|
return -EINVAL;
|
|
|
|
#ifdef CONFIG_USB_OTG_UTILS
|
|
if (tegra->transceiver) {
|
|
otg_set_host(tegra->transceiver, NULL);
|
|
otg_put_transceiver(tegra->transceiver);
|
|
}
|
|
#endif
|
|
|
|
usb_remove_hcd(hcd);
|
|
usb_put_hcd(hcd);
|
|
|
|
tegra_usb_phy_close(tegra->phy);
|
|
iounmap(hcd->regs);
|
|
|
|
clk_disable(tegra->clk);
|
|
clk_put(tegra->clk);
|
|
|
|
clk_disable(tegra->emc_clk);
|
|
clk_put(tegra->emc_clk);
|
|
|
|
kfree(tegra);
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
|
|
struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
|
|
|
|
if (hcd->driver->shutdown)
|
|
hcd->driver->shutdown(hcd);
|
|
}
|
|
|
|
static struct platform_driver tegra_ehci_driver = {
|
|
.probe = tegra_ehci_probe,
|
|
.remove = tegra_ehci_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = tegra_ehci_suspend,
|
|
.resume = tegra_ehci_resume,
|
|
#endif
|
|
.shutdown = tegra_ehci_hcd_shutdown,
|
|
.driver = {
|
|
.name = "tegra-ehci",
|
|
}
|
|
};
|