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31eb6b4386
Add connect/disconnect helper to assign private struct to the DSA switch. Add support for Ethernet mgmt and MIB if the DSA driver provide an handler to correctly parse and elaborate the data. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __TAG_QCA_H
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#define __TAG_QCA_H
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#define QCA_HDR_LEN 2
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#define QCA_HDR_VERSION 0x2
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#define QCA_HDR_RECV_VERSION GENMASK(15, 14)
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#define QCA_HDR_RECV_PRIORITY GENMASK(13, 11)
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#define QCA_HDR_RECV_TYPE GENMASK(10, 6)
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#define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3)
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#define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0)
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/* Packet type for recv */
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#define QCA_HDR_RECV_TYPE_NORMAL 0x0
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#define QCA_HDR_RECV_TYPE_MIB 0x1
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#define QCA_HDR_RECV_TYPE_RW_REG_ACK 0x2
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#define QCA_HDR_XMIT_VERSION GENMASK(15, 14)
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#define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11)
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#define QCA_HDR_XMIT_CONTROL GENMASK(10, 8)
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#define QCA_HDR_XMIT_FROM_CPU BIT(7)
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#define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0)
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/* Packet type for xmit */
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#define QCA_HDR_XMIT_TYPE_NORMAL 0x0
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#define QCA_HDR_XMIT_TYPE_RW_REG 0x1
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/* Check code for a valid mgmt packet. Switch will ignore the packet
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* with this wrong.
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*/
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#define QCA_HDR_MGMT_CHECK_CODE_VAL 0x5
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/* Specific define for in-band MDIO read/write with Ethernet packet */
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#define QCA_HDR_MGMT_SEQ_LEN 4 /* 4 byte for the seq */
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#define QCA_HDR_MGMT_COMMAND_LEN 4 /* 4 byte for the command */
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#define QCA_HDR_MGMT_DATA1_LEN 4 /* First 4 byte for the mdio data */
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#define QCA_HDR_MGMT_HEADER_LEN (QCA_HDR_MGMT_SEQ_LEN + \
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QCA_HDR_MGMT_COMMAND_LEN + \
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QCA_HDR_MGMT_DATA1_LEN)
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#define QCA_HDR_MGMT_DATA2_LEN 12 /* Other 12 byte for the mdio data */
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#define QCA_HDR_MGMT_PADDING_LEN 34 /* Padding to reach the min Ethernet packet */
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#define QCA_HDR_MGMT_PKT_LEN (QCA_HDR_MGMT_HEADER_LEN + \
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QCA_HDR_LEN + \
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QCA_HDR_MGMT_DATA2_LEN + \
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QCA_HDR_MGMT_PADDING_LEN)
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#define QCA_HDR_MGMT_SEQ_NUM GENMASK(31, 0) /* 63, 32 */
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#define QCA_HDR_MGMT_CHECK_CODE GENMASK(31, 29) /* 31, 29 */
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#define QCA_HDR_MGMT_CMD BIT(28) /* 28 */
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#define QCA_HDR_MGMT_LENGTH GENMASK(23, 20) /* 23, 20 */
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#define QCA_HDR_MGMT_ADDR GENMASK(18, 0) /* 18, 0 */
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/* Special struct emulating a Ethernet header */
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struct qca_mgmt_ethhdr {
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u32 command; /* command bit 31:0 */
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u32 seq; /* seq 63:32 */
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u32 mdio_data; /* first 4byte mdio */
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__be16 hdr; /* qca hdr */
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} __packed;
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enum mdio_cmd {
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MDIO_WRITE = 0x0,
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MDIO_READ
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};
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struct mib_ethhdr {
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u32 data[3]; /* first 3 mib counter */
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__be16 hdr; /* qca hdr */
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} __packed;
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struct qca_tagger_data {
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void (*rw_reg_ack_handler)(struct dsa_switch *ds,
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struct sk_buff *skb);
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void (*mib_autocast_handler)(struct dsa_switch *ds,
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struct sk_buff *skb);
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};
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#endif /* __TAG_QCA_H */
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