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There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf -a|grep -i cache' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC 2 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC 4 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 524288 LEVEL2_CACHE_ASSOC 8 LEVEL2_CACHE_LINESIZE 64 LEVEL3_CACHE_SIZE 4194304 LEVEL3_CACHE_ASSOC 16 LEVEL3_CACHE_LINESIZE 64 LEVEL4_CACHE_SIZE 0 LEVEL4_CACHE_ASSOC 0 LEVEL4_CACHE_LINESIZE 0 Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-8-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
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/*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _UAPI_ASM_RISCV_AUXVEC_H
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#define _UAPI_ASM_RISCV_AUXVEC_H
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/* vDSO location */
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#define AT_SYSINFO_EHDR 33
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/*
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* The set of entries below represent more extensive information
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* about the caches, in the form of two entry per cache type,
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* one entry containing the cache size in bytes, and the other
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* containing the cache line size in bytes in the bottom 16 bits
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* and the cache associativity in the next 16 bits.
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*
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* The associativity is such that if N is the 16-bit value, the
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* cache is N way set associative. A value if 0xffff means fully
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* associative, a value of 1 means directly mapped.
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*
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* For all these fields, a value of 0 means that the information
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* is not known.
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*/
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#define AT_L1I_CACHESIZE 40
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#define AT_L1I_CACHEGEOMETRY 41
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#define AT_L1D_CACHESIZE 42
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#define AT_L1D_CACHEGEOMETRY 43
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#define AT_L2_CACHESIZE 44
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#define AT_L2_CACHEGEOMETRY 45
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#define AT_L3_CACHESIZE 46
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#define AT_L3_CACHEGEOMETRY 47
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/* entries in ARCH_DLINFO */
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#define AT_VECTOR_SIZE_ARCH 9
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#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
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