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9bec2b9c61
Currently, unbinding a CCU driver unmaps the device's MMIO region, while leaving its clocks/resets and their providers registered. This can cause a page fault later when some clock operation tries to perform MMIO. Fix this by separating the CCU initialization from the memory allocation, and then using a devres callback to unregister the clocks and resets. This also fixes a memory leak of the `struct ccu_reset`, and uses the correct owner (the specific platform driver) for the clocks and resets. Early OF clock providers are never unregistered, and limited error handling is possible, so they are mostly unchanged. The error reporting is made more consistent by moving the message inside of_sunxi_ccu_probe. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210901050526.45673-2-samuel@sholland.org
250 lines
7.1 KiB
C
250 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu_nm.h"
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#include "ccu-sun50i-h6-r.h"
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/*
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* Information about AR100 and AHB/APB clocks in R_CCU are gathered from
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* clock definitions in the BSP source code.
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*/
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static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
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"iosc", "pll-periph0" };
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static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
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{ .index = 3, .shift = 0, .width = 5 },
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};
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static struct ccu_div ar100_clk = {
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.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
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.mux = {
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.shift = 24,
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.width = 2,
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.var_predivs = ar100_r_apb2_predivs,
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.n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
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},
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.common = {
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.reg = 0x000,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS("ar100",
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ar100_r_apb2_parents,
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&ccu_div_ops,
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0),
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},
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};
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static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
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static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
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static struct ccu_div r_apb2_clk = {
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.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
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.mux = {
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.shift = 24,
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.width = 2,
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.var_predivs = ar100_r_apb2_predivs,
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.n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
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},
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.common = {
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.reg = 0x010,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS("r-apb2",
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ar100_r_apb2_parents,
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&ccu_div_ops,
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0),
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},
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};
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/*
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* Information about the gate/resets are gathered from the clock header file
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* in the BSP source code, although most of them are unused. The existence
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* of the hardware block is verified with "3.1 Memory Mapping" chapter in
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* "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
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* with "3.3.2.1 System Bus Tree" chapter inthe same document.
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*/
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static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
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0x11c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
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0x12c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1",
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0x13c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
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0x18c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
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0x19c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb2_rsb_clk, "r-apb2-rsb", "r-apb2",
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0x1bc, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
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0x1cc, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
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0x1ec, BIT(0), 0);
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/* Information of IR(RX) mod clock is gathered from BSP source code */
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static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
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static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
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r_mod0_default_parents, 0x1c0,
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0, 5, /* M */
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8, 2, /* P */
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24, 1, /* mux */
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BIT(31), /* gate */
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0);
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/*
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* BSP didn't use the 1-wire function at all now, and the information about
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* this mod clock is guessed from the IR mod clock above. The existence of
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* this mod clock is proven by BSP clock header, and the dividers are verified
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* by contents in the 1-wire related chapter of the User Manual.
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*/
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static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
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r_mod0_default_parents, 0x1e0,
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0, 5, /* M */
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8, 2, /* P */
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24, 1, /* mux */
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BIT(31), /* gate */
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0);
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static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
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&ar100_clk.common,
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&r_apb1_clk.common,
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&r_apb2_clk.common,
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&r_apb1_timer_clk.common,
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&r_apb1_twd_clk.common,
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&r_apb1_pwm_clk.common,
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&r_apb2_uart_clk.common,
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&r_apb2_i2c_clk.common,
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&r_apb2_rsb_clk.common,
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&r_apb1_ir_clk.common,
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&r_apb1_w1_clk.common,
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&ir_clk.common,
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&w1_clk.common,
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};
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static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
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&r_apb1_clk.common,
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&r_apb2_clk.common,
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&r_apb1_twd_clk.common,
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&r_apb2_i2c_clk.common,
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&r_apb2_rsb_clk.common,
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&r_apb1_ir_clk.common,
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&ir_clk.common,
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};
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static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
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.hws = {
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[CLK_AR100] = &ar100_clk.common.hw,
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[CLK_R_AHB] = &r_ahb_clk.hw,
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[CLK_R_APB1] = &r_apb1_clk.common.hw,
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[CLK_R_APB2] = &r_apb2_clk.common.hw,
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[CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
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[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
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[CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
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[CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
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[CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
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[CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
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[CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
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[CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
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[CLK_IR] = &ir_clk.common.hw,
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[CLK_W1] = &w1_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
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.hws = {
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[CLK_R_AHB] = &r_ahb_clk.hw,
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[CLK_R_APB1] = &r_apb1_clk.common.hw,
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[CLK_R_APB2] = &r_apb2_clk.common.hw,
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[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
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[CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
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[CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
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[CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
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[CLK_IR] = &ir_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
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[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
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[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
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[RST_R_APB1_PWM] = { 0x13c, BIT(16) },
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[RST_R_APB2_UART] = { 0x18c, BIT(16) },
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[RST_R_APB2_I2C] = { 0x19c, BIT(16) },
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[RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
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[RST_R_APB1_IR] = { 0x1cc, BIT(16) },
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[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
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};
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static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
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[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
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[RST_R_APB2_I2C] = { 0x19c, BIT(16) },
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[RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
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[RST_R_APB1_IR] = { 0x1cc, BIT(16) },
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};
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static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
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.ccu_clks = sun50i_h6_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
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.hw_clks = &sun50i_h6_r_hw_clks,
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.resets = sun50i_h6_r_ccu_resets,
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.num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
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};
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static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
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.ccu_clks = sun50i_h616_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
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.hw_clks = &sun50i_h616_r_hw_clks,
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.resets = sun50i_h616_r_ccu_resets,
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.num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
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};
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static void __init sunxi_r_ccu_init(struct device_node *node,
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const struct sunxi_ccu_desc *desc)
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{
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void __iomem *reg;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg)) {
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pr_err("%pOF: Could not map the clock registers\n", node);
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return;
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}
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of_sunxi_ccu_probe(node, reg, desc);
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}
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static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
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{
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sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
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}
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CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
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sun50i_h6_r_ccu_setup);
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static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
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{
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sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc);
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}
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CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
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sun50i_h616_r_ccu_setup);
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