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![Douglas Thompson](/assets/img/avatar_default.png)
This is a large patch to refactor the original EDAC module in the kernel and to break it up into better file granularity, such that each source file contains a given subsystem of the EDAC CORE. Originally, the EDAC 'core' was contained in one source file: edac_mc.c with it corresponding edac_mc.h file. Now, there are the following files: edac_module.c The main module init/exit function and other overhead edac_mc.c Code handling the edac_mc class of object edac_mc_sysfs.c Code handling for sysfs presentation edac_pci_sysfs.c Code handling for PCI sysfs presentation edac_core.h CORE .h include file for 'edac_mc' and 'edac_device' drivers edac_module.h Internal CORE .h include file This forms a foundation upon which a later patch can create the 'edac_device' class of object code in a new file 'edac_device.c'. Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
361 lines
8.9 KiB
C
361 lines
8.9 KiB
C
/* edac_mc kernel module
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* (C) 2005, 2006 Linux Networx (http://lnxi.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written Doug Thompson <norsk5@xmission.com>
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*
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*/
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#include <linux/module.h>
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#include <linux/sysdev.h>
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#include <linux/ctype.h>
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#include "edac_mc.h"
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#include "edac_module.h"
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#ifdef CONFIG_PCI
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static int check_pci_parity = 0; /* default YES check PCI parity */
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static int panic_on_pci_parity; /* default no panic on PCI Parity */
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static atomic_t pci_parity_count = ATOMIC_INIT(0);
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static struct kobject edac_pci_kobj; /* /sys/devices/system/edac/pci */
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static struct completion edac_pci_kobj_complete;
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static ssize_t edac_pci_int_show(void *ptr, char *buffer)
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{
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int *value = ptr;
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return sprintf(buffer,"%d\n",*value);
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}
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static ssize_t edac_pci_int_store(void *ptr, const char *buffer, size_t count)
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{
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int *value = ptr;
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if (isdigit(*buffer))
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*value = simple_strtoul(buffer,NULL,0);
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return count;
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}
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struct edac_pci_dev_attribute {
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struct attribute attr;
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void *value;
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ssize_t (*show)(void *,char *);
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ssize_t (*store)(void *, const char *,size_t);
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};
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/* Set of show/store abstract level functions for PCI Parity object */
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static ssize_t edac_pci_dev_show(struct kobject *kobj, struct attribute *attr,
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char *buffer)
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{
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struct edac_pci_dev_attribute *edac_pci_dev;
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edac_pci_dev= (struct edac_pci_dev_attribute*)attr;
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if (edac_pci_dev->show)
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return edac_pci_dev->show(edac_pci_dev->value, buffer);
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return -EIO;
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}
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static ssize_t edac_pci_dev_store(struct kobject *kobj,
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struct attribute *attr, const char *buffer, size_t count)
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{
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struct edac_pci_dev_attribute *edac_pci_dev;
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edac_pci_dev= (struct edac_pci_dev_attribute*)attr;
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if (edac_pci_dev->show)
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return edac_pci_dev->store(edac_pci_dev->value, buffer, count);
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return -EIO;
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}
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static struct sysfs_ops edac_pci_sysfs_ops = {
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.show = edac_pci_dev_show,
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.store = edac_pci_dev_store
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};
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#define EDAC_PCI_ATTR(_name,_mode,_show,_store) \
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static struct edac_pci_dev_attribute edac_pci_attr_##_name = { \
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.attr = {.name = __stringify(_name), .mode = _mode }, \
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.value = &_name, \
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.show = _show, \
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.store = _store, \
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};
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#define EDAC_PCI_STRING_ATTR(_name,_data,_mode,_show,_store) \
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static struct edac_pci_dev_attribute edac_pci_attr_##_name = { \
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.attr = {.name = __stringify(_name), .mode = _mode }, \
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.value = _data, \
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.show = _show, \
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.store = _store, \
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};
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/* PCI Parity control files */
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EDAC_PCI_ATTR(check_pci_parity, S_IRUGO|S_IWUSR, edac_pci_int_show,
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edac_pci_int_store);
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EDAC_PCI_ATTR(panic_on_pci_parity, S_IRUGO|S_IWUSR, edac_pci_int_show,
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edac_pci_int_store);
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EDAC_PCI_ATTR(pci_parity_count, S_IRUGO, edac_pci_int_show, NULL);
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/* Base Attributes of the memory ECC object */
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static struct edac_pci_dev_attribute *edac_pci_attr[] = {
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&edac_pci_attr_check_pci_parity,
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&edac_pci_attr_panic_on_pci_parity,
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&edac_pci_attr_pci_parity_count,
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NULL,
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};
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/* No memory to release */
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static void edac_pci_release(struct kobject *kobj)
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{
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debugf1("%s()\n", __func__);
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complete(&edac_pci_kobj_complete);
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}
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static struct kobj_type ktype_edac_pci = {
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.release = edac_pci_release,
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.sysfs_ops = &edac_pci_sysfs_ops,
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.default_attrs = (struct attribute **) edac_pci_attr,
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};
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/**
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* edac_sysfs_pci_setup()
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*
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* setup the sysfs for EDAC PCI attributes
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* assumes edac_class has already been initialized
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*/
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int edac_sysfs_pci_setup(void)
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{
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int err;
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struct sysdev_class *edac_class;
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debugf1("%s()\n", __func__);
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edac_class = edac_get_edac_class();
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memset(&edac_pci_kobj, 0, sizeof(edac_pci_kobj));
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edac_pci_kobj.parent = &edac_class->kset.kobj;
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edac_pci_kobj.ktype = &ktype_edac_pci;
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err = kobject_set_name(&edac_pci_kobj, "pci");
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if (!err) {
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/* Instanstiate the pci object */
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/* FIXME: maybe new sysdev_create_subdir() */
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err = kobject_register(&edac_pci_kobj);
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if (err)
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debugf1("Failed to register '.../edac/pci'\n");
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else
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debugf1("Registered '.../edac/pci' kobject\n");
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}
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return err;
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}
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/*
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* edac_sysfs_pci_teardown
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*
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* perform the sysfs teardown for the PCI attributes
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*/
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void edac_sysfs_pci_teardown(void)
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{
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debugf0("%s()\n", __func__);
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init_completion(&edac_pci_kobj_complete);
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kobject_unregister(&edac_pci_kobj);
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wait_for_completion(&edac_pci_kobj_complete);
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}
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static u16 get_pci_parity_status(struct pci_dev *dev, int secondary)
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{
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int where;
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u16 status;
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where = secondary ? PCI_SEC_STATUS : PCI_STATUS;
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pci_read_config_word(dev, where, &status);
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/* If we get back 0xFFFF then we must suspect that the card has been
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* pulled but the Linux PCI layer has not yet finished cleaning up.
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* We don't want to report on such devices
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*/
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if (status == 0xFFFF) {
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u32 sanity;
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pci_read_config_dword(dev, 0, &sanity);
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if (sanity == 0xFFFFFFFF)
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return 0;
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}
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status &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
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PCI_STATUS_PARITY;
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if (status)
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/* reset only the bits we are interested in */
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pci_write_config_word(dev, where, status);
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return status;
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}
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typedef void (*pci_parity_check_fn_t) (struct pci_dev *dev);
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/* Clear any PCI parity errors logged by this device. */
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static void edac_pci_dev_parity_clear(struct pci_dev *dev)
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{
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u8 header_type;
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get_pci_parity_status(dev, 0);
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/* read the device TYPE, looking for bridges */
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
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if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE)
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get_pci_parity_status(dev, 1);
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}
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/*
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* PCI Parity polling
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*
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*/
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static void edac_pci_dev_parity_test(struct pci_dev *dev)
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{
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u16 status;
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u8 header_type;
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/* read the STATUS register on this device
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*/
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status = get_pci_parity_status(dev, 0);
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debugf2("PCI STATUS= 0x%04x %s\n", status, dev->dev.bus_id );
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/* check the status reg for errors */
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if (status) {
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if (status & (PCI_STATUS_SIG_SYSTEM_ERROR))
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edac_printk(KERN_CRIT, EDAC_PCI,
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"Signaled System Error on %s\n",
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pci_name(dev));
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if (status & (PCI_STATUS_PARITY)) {
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edac_printk(KERN_CRIT, EDAC_PCI,
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"Master Data Parity Error on %s\n",
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pci_name(dev));
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atomic_inc(&pci_parity_count);
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}
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if (status & (PCI_STATUS_DETECTED_PARITY)) {
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edac_printk(KERN_CRIT, EDAC_PCI,
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"Detected Parity Error on %s\n",
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pci_name(dev));
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atomic_inc(&pci_parity_count);
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}
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}
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/* read the device TYPE, looking for bridges */
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
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debugf2("PCI HEADER TYPE= 0x%02x %s\n", header_type, dev->dev.bus_id );
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if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
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/* On bridges, need to examine secondary status register */
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status = get_pci_parity_status(dev, 1);
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debugf2("PCI SEC_STATUS= 0x%04x %s\n",
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status, dev->dev.bus_id );
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/* check the secondary status reg for errors */
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if (status) {
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if (status & (PCI_STATUS_SIG_SYSTEM_ERROR))
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edac_printk(KERN_CRIT, EDAC_PCI, "Bridge "
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"Signaled System Error on %s\n",
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pci_name(dev));
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if (status & (PCI_STATUS_PARITY)) {
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edac_printk(KERN_CRIT, EDAC_PCI, "Bridge "
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"Master Data Parity Error on "
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"%s\n", pci_name(dev));
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atomic_inc(&pci_parity_count);
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}
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if (status & (PCI_STATUS_DETECTED_PARITY)) {
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edac_printk(KERN_CRIT, EDAC_PCI, "Bridge "
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"Detected Parity Error on %s\n",
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pci_name(dev));
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atomic_inc(&pci_parity_count);
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}
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}
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}
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}
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/*
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* pci_dev parity list iterator
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* Scan the PCI device list for one iteration, looking for SERRORs
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* Master Parity ERRORS or Parity ERRORs on primary or secondary devices
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*/
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static inline void edac_pci_dev_parity_iterator(pci_parity_check_fn_t fn)
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{
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struct pci_dev *dev = NULL;
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/* request for kernel access to the next PCI device, if any,
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* and while we are looking at it have its reference count
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* bumped until we are done with it
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*/
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while((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
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fn(dev);
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}
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}
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/*
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* edac_pci_do_parity_check
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*
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* performs the actual PCI parity check operation
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*/
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void edac_pci_do_parity_check(void)
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{
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unsigned long flags;
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int before_count;
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debugf3("%s()\n", __func__);
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if (!check_pci_parity)
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return;
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before_count = atomic_read(&pci_parity_count);
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/* scan all PCI devices looking for a Parity Error on devices and
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* bridges
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*/
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local_irq_save(flags);
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edac_pci_dev_parity_iterator(edac_pci_dev_parity_test);
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local_irq_restore(flags);
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/* Only if operator has selected panic on PCI Error */
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if (panic_on_pci_parity) {
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/* If the count is different 'after' from 'before' */
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if (before_count != atomic_read(&pci_parity_count))
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panic("EDAC: PCI Parity Error");
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}
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}
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void edac_pci_clear_parity_errors(void)
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{
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/* Clear any PCI bus parity errors that devices initially have logged
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* in their registers.
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*/
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edac_pci_dev_parity_iterator(edac_pci_dev_parity_clear);
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}
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/*
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* Define the PCI parameter to the module
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*/
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module_param(check_pci_parity, int, 0644);
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MODULE_PARM_DESC(check_pci_parity, "Check for PCI bus parity errors: 0=off 1=on");
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module_param(panic_on_pci_parity, int, 0644);
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MODULE_PARM_DESC(panic_on_pci_parity, "Panic on PCI Bus Parity error: 0=off 1=on");
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#endif /* CONFIG_PCI */
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