Artemy Kovalyov 7d0cc6edcc IB/mlx5: Add MR cache for large UMR regions ... In this change we turn mlx5_ib_update_mtt() into generic mlx5_ib_update_xlt() to perfrom HCA translation table modifiactions supporting both atomic and process contexts and not limited by number of modified entries. Using this function we increase preallocated MRs up to 16GB. Signed-off-by: Artemy Kovalyov <artemyko@mellanox.com> Signed-off-by: Leon Romanovsky <leon@kernel.org> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2017-01-02 15:51:20 -05:00
..
cmd.h
cq.h	{net,IB}/mlx5: CQ commands via mlx5 ifc	2016-08-14 14:39:15 +03:00
device.h	net/mlx5: Add MPCNT register infrastructure	2016-11-18 12:08:58 -05:00
doorbell.h
driver.h	IB/mlx5: Add MR cache for large UMR regions	2017-01-02 15:51:20 -05:00
fs.h	net/mlx5: Support encap id when setting new steering entry	2016-11-09 13:41:56 -05:00
mlx5_ifc.h	net/mlx5: Support new MR features	2017-01-02 15:51:20 -05:00
port.h	net/mlx5: Add DCBX firmware commands support	2016-11-28 15:09:35 -05:00
qp.h	IB/mlx5: Refactor UMR post send format	2017-01-02 15:51:20 -05:00
srq.h	net/mlx5: Ensure SRQ physical address structure endianness	2016-10-30 15:43:10 +02:00
transobj.h	IB/mlx5: Support setting Ethernet priority for Raw Packet QPs	2016-01-21 12:01:09 -05:00
vport.h	net/mlx5: Enable to query min inline for a specific vport	2016-11-24 16:01:14 -05:00