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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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66229b2005
This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
165 lines
7.3 KiB
C
165 lines
7.3 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef RV730_H
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#define RV730_H
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#define CG_SPLL_FUNC_CNTL 0x600
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#define SPLL_RESET (1 << 0)
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#define SPLL_SLEEP (1 << 1)
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#define SPLL_DIVEN (1 << 2)
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#define SPLL_BYPASS_EN (1 << 3)
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#define SPLL_REF_DIV(x) ((x) << 4)
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#define SPLL_REF_DIV_MASK (0x3f << 4)
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#define SPLL_HILEN(x) ((x) << 12)
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#define SPLL_HILEN_MASK (0xf << 12)
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#define SPLL_LOLEN(x) ((x) << 16)
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#define SPLL_LOLEN_MASK (0xf << 16)
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#define CG_SPLL_FUNC_CNTL_2 0x604
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#define SCLK_MUX_SEL(x) ((x) << 0)
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#define SCLK_MUX_SEL_MASK (0x1ff << 0)
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#define CG_SPLL_FUNC_CNTL_3 0x608
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#define SPLL_FB_DIV(x) ((x) << 0)
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#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
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#define SPLL_DITHEN (1 << 28)
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#define CG_MPLL_FUNC_CNTL 0x624
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#define MPLL_RESET (1 << 0)
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#define MPLL_SLEEP (1 << 1)
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#define MPLL_DIVEN (1 << 2)
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#define MPLL_BYPASS_EN (1 << 3)
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#define MPLL_REF_DIV(x) ((x) << 4)
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#define MPLL_REF_DIV_MASK (0x3f << 4)
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#define MPLL_HILEN(x) ((x) << 12)
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#define MPLL_HILEN_MASK (0xf << 12)
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#define MPLL_LOLEN(x) ((x) << 16)
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#define MPLL_LOLEN_MASK (0xf << 16)
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#define CG_MPLL_FUNC_CNTL_2 0x628
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#define MCLK_MUX_SEL(x) ((x) << 0)
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#define MCLK_MUX_SEL_MASK (0x1ff << 0)
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#define CG_MPLL_FUNC_CNTL_3 0x62c
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#define MPLL_FB_DIV(x) ((x) << 0)
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#define MPLL_FB_DIV_MASK (0x3ffffff << 0)
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#define MPLL_DITHEN (1 << 28)
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#define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634
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#define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638
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#define GENERAL_PWRMGT 0x63c
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# define GLOBAL_PWRMGT_EN (1 << 0)
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# define STATIC_PM_EN (1 << 1)
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# define THERMAL_PROTECTION_DIS (1 << 2)
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# define THERMAL_PROTECTION_TYPE (1 << 3)
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# define ENABLE_GEN2PCIE (1 << 4)
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# define ENABLE_GEN2XSP (1 << 5)
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# define SW_SMIO_INDEX(x) ((x) << 6)
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# define SW_SMIO_INDEX_MASK (3 << 6)
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# define LOW_VOLT_D2_ACPI (1 << 8)
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# define LOW_VOLT_D3_ACPI (1 << 9)
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# define VOLT_PWRMGT_EN (1 << 10)
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# define BACKBIAS_PAD_EN (1 << 18)
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# define BACKBIAS_VALUE (1 << 19)
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# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
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# define AC_DC_SW (1 << 24)
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#define SCLK_PWRMGT_CNTL 0x644
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# define SCLK_PWRMGT_OFF (1 << 0)
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# define SCLK_LOW_D1 (1 << 1)
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# define FIR_RESET (1 << 4)
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# define FIR_FORCE_TREND_SEL (1 << 5)
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# define FIR_TREND_MODE (1 << 6)
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# define DYN_GFX_CLK_OFF_EN (1 << 7)
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# define GFX_CLK_FORCE_ON (1 << 8)
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# define GFX_CLK_REQUEST_OFF (1 << 9)
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# define GFX_CLK_FORCE_OFF (1 << 10)
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# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
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# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
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# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
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#define TCI_MCLK_PWRMGT_CNTL 0x648
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# define MPLL_PWRMGT_OFF (1 << 5)
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# define DLL_READY (1 << 6)
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# define MC_INT_CNTL (1 << 7)
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# define MRDCKA_SLEEP (1 << 8)
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# define MRDCKB_SLEEP (1 << 9)
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# define MRDCKC_SLEEP (1 << 10)
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# define MRDCKD_SLEEP (1 << 11)
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# define MRDCKE_SLEEP (1 << 12)
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# define MRDCKF_SLEEP (1 << 13)
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# define MRDCKG_SLEEP (1 << 14)
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# define MRDCKH_SLEEP (1 << 15)
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# define MRDCKA_RESET (1 << 16)
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# define MRDCKB_RESET (1 << 17)
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# define MRDCKC_RESET (1 << 18)
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# define MRDCKD_RESET (1 << 19)
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# define MRDCKE_RESET (1 << 20)
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# define MRDCKF_RESET (1 << 21)
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# define MRDCKG_RESET (1 << 22)
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# define MRDCKH_RESET (1 << 23)
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# define DLL_READY_READ (1 << 24)
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# define USE_DISPLAY_GAP (1 << 25)
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# define USE_DISPLAY_URGENT_NORMAL (1 << 26)
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# define MPLL_TURNOFF_D2 (1 << 28)
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#define TCI_DLL_CNTL 0x64c
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#define CG_PG_CNTL 0x858
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# define PWRGATE_ENABLE (1 << 0)
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#define CG_AT 0x6d4
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#define CG_R(x) ((x) << 0)
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#define CG_R_MASK (0xffff << 0)
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#define CG_L(x) ((x) << 16)
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#define CG_L_MASK (0xffff << 16)
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#define CG_SPLL_SPREAD_SPECTRUM 0x790
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#define SSEN (1 << 0)
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#define CLK_S(x) ((x) << 4)
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#define CLK_S_MASK (0xfff << 4)
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#define CG_SPLL_SPREAD_SPECTRUM_2 0x794
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#define CLK_V(x) ((x) << 0)
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#define CLK_V_MASK (0x3ffffff << 0)
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#define MC_ARB_DRAM_TIMING 0x2774
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#define MC_ARB_DRAM_TIMING2 0x2778
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#define MC_ARB_RFSH_RATE 0x27b0
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#define POWERMODE0(x) ((x) << 0)
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#define POWERMODE0_MASK (0xff << 0)
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#define POWERMODE1(x) ((x) << 8)
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#define POWERMODE1_MASK (0xff << 8)
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#define POWERMODE2(x) ((x) << 16)
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#define POWERMODE2_MASK (0xff << 16)
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#define POWERMODE3(x) ((x) << 24)
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#define POWERMODE3_MASK (0xff << 24)
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#define MC_ARB_DRAM_TIMING_1 0x27f0
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#define MC_ARB_DRAM_TIMING_2 0x27f4
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#define MC_ARB_DRAM_TIMING_3 0x27f8
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#define MC_ARB_DRAM_TIMING2_1 0x27fc
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#define MC_ARB_DRAM_TIMING2_2 0x2800
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#define MC_ARB_DRAM_TIMING2_3 0x2804
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#define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978
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#define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c
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#define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980
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#define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984
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#endif
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