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![Stephen Boyd](/assets/img/avatar_default.png)
Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Add support for a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Non-DT platforms can add support by directly updating the chip->valid_mask. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Timur Tabi <timur@codeaurora.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
584 lines
17 KiB
C
584 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_GPIO_DRIVER_H
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#define __LINUX_GPIO_DRIVER_H
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#include <linux/device.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/lockdep.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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struct gpio_desc;
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struct of_phandle_args;
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struct device_node;
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struct seq_file;
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struct gpio_device;
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struct module;
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#ifdef CONFIG_GPIOLIB
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#ifdef CONFIG_GPIOLIB_IRQCHIP
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/**
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* struct gpio_irq_chip - GPIO interrupt controller
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*/
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struct gpio_irq_chip {
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/**
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* @chip:
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*
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* GPIO IRQ chip implementation, provided by GPIO driver.
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*/
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struct irq_chip *chip;
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/**
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* @domain:
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*
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* Interrupt translation domain; responsible for mapping between GPIO
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* hwirq number and Linux IRQ number.
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*/
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struct irq_domain *domain;
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/**
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* @domain_ops:
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*
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* Table of interrupt domain operations for this IRQ chip.
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*/
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const struct irq_domain_ops *domain_ops;
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/**
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* @handler:
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*
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* The IRQ handler to use (often a predefined IRQ core function) for
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* GPIO IRQs, provided by GPIO driver.
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*/
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irq_flow_handler_t handler;
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/**
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* @default_type:
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*
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* Default IRQ triggering type applied during GPIO driver
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* initialization, provided by GPIO driver.
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*/
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unsigned int default_type;
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/**
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* @lock_key:
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*
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* Per GPIO IRQ chip lockdep classes.
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*/
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struct lock_class_key *lock_key;
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struct lock_class_key *request_key;
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/**
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* @parent_handler:
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*
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* The interrupt handler for the GPIO chip's parent interrupts, may be
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* NULL if the parent interrupts are nested rather than cascaded.
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*/
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irq_flow_handler_t parent_handler;
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/**
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* @parent_handler_data:
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*
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* Data associated, and passed to, the handler for the parent
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* interrupt.
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*/
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void *parent_handler_data;
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/**
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* @num_parents:
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*
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* The number of interrupt parents of a GPIO chip.
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*/
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unsigned int num_parents;
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/**
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* @parents:
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*
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* A list of interrupt parents of a GPIO chip. This is owned by the
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* driver, so the core will only reference this list, not modify it.
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*/
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unsigned int *parents;
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/**
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* @map:
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*
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* A list of interrupt parents for each line of a GPIO chip.
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*/
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unsigned int *map;
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/**
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* @threaded:
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*
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* True if set the interrupt handling uses nested threads.
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*/
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bool threaded;
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/**
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* @need_valid_mask:
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*
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* If set core allocates @valid_mask with all bits set to one.
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*/
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bool need_valid_mask;
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/**
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* @valid_mask:
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*
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* If not %NULL holds bitmask of GPIOs which are valid to be included
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* in IRQ domain of the chip.
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*/
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unsigned long *valid_mask;
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/**
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* @first:
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*
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* Required for static IRQ allocation. If set, irq_domain_add_simple()
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* will allocate and map all IRQs during initialization.
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*/
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unsigned int first;
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};
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static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)
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{
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return container_of(chip, struct gpio_irq_chip, chip);
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}
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#endif
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/**
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* struct gpio_chip - abstract a GPIO controller
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* @label: a functional name for the GPIO device, such as a part
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* number or the name of the SoC IP-block implementing it.
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* @gpiodev: the internal state holder, opaque struct
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* @parent: optional parent device providing the GPIOs
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* @owner: helps prevent removal of modules exporting active GPIOs
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* @request: optional hook for chip-specific activation, such as
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* enabling module power and clock; may sleep
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* @free: optional hook for chip-specific deactivation, such as
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* disabling module power and clock; may sleep
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* @get_direction: returns direction for signal "offset", 0=out, 1=in,
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* (same as GPIOF_DIR_XXX), or negative error
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* @direction_input: configures signal "offset" as input, or returns error
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* @direction_output: configures signal "offset" as output, or returns error
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* @get: returns value for signal "offset", 0=low, 1=high, or negative error
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* @get_multiple: reads values for multiple signals defined by "mask" and
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* stores them in "bits", returns 0 on success or negative error
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* @set: assigns output value for signal "offset"
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* @set_multiple: assigns output values for multiple signals defined by "mask"
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* @set_config: optional hook for all kinds of settings. Uses the same
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* packed config format as generic pinconf.
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* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
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* implementation may not sleep
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* @dbg_show: optional routine to show contents in debugfs; default code
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* will be used when this is omitted, but custom code can show extra
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* state (such as pullup/pulldown configuration).
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* @base: identifies the first GPIO number handled by this chip;
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* or, if negative during registration, requests dynamic ID allocation.
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* DEPRECATION: providing anything non-negative and nailing the base
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* offset of GPIO chips is deprecated. Please pass -1 as base to
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* let gpiolib select the chip base in all possible cases. We want to
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* get rid of the static GPIO number space in the long run.
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* @ngpio: the number of GPIOs handled by this controller; the last GPIO
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* handled is (base + ngpio - 1).
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* @names: if set, must be an array of strings to use as alternative
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* names for the GPIOs in this chip. Any entry in the array
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* may be NULL if there is no alias for the GPIO, however the
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* array must be @ngpio entries long. A name can include a single printk
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* format specifier for an unsigned int. It is substituted by the actual
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* number of the gpio.
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* @can_sleep: flag must be set iff get()/set() methods sleep, as they
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* must while accessing GPIO expander chips over I2C or SPI. This
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* implies that if the chip supports IRQs, these IRQs need to be threaded
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* as the chip access may sleep when e.g. reading out the IRQ status
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* registers.
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* @read_reg: reader function for generic GPIO
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* @write_reg: writer function for generic GPIO
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* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
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* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
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* generic GPIO core. It is for internal housekeeping only.
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* @reg_dat: data (in) register for generic GPIO
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* @reg_set: output set register (out=high) for generic GPIO
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* @reg_clr: output clear register (out=low) for generic GPIO
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* @reg_dir: direction setting register for generic GPIO
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* @bgpio_bits: number of register bits used for a generic GPIO i.e.
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* <register width> * 8
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* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
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* shadowed and real data registers writes together.
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* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
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* safely.
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* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
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* direction safely.
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*
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* A gpio_chip can help platforms abstract various sources of GPIOs so
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* they can all be accessed through a common programing interface.
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* Example sources would be SOC controllers, FPGAs, multifunction
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* chips, dedicated GPIO expanders, and so on.
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*
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* Each chip controls a number of signals, identified in method calls
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* by "offset" values in the range 0..(@ngpio - 1). When those signals
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* are referenced through calls like gpio_get_value(gpio), the offset
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* is calculated by subtracting @base from the gpio number.
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*/
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struct gpio_chip {
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const char *label;
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struct gpio_device *gpiodev;
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struct device *parent;
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struct module *owner;
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int (*request)(struct gpio_chip *chip,
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unsigned offset);
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void (*free)(struct gpio_chip *chip,
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unsigned offset);
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int (*get_direction)(struct gpio_chip *chip,
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unsigned offset);
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int (*direction_input)(struct gpio_chip *chip,
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unsigned offset);
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int (*direction_output)(struct gpio_chip *chip,
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unsigned offset, int value);
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int (*get)(struct gpio_chip *chip,
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unsigned offset);
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int (*get_multiple)(struct gpio_chip *chip,
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unsigned long *mask,
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unsigned long *bits);
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void (*set)(struct gpio_chip *chip,
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unsigned offset, int value);
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void (*set_multiple)(struct gpio_chip *chip,
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unsigned long *mask,
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unsigned long *bits);
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int (*set_config)(struct gpio_chip *chip,
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unsigned offset,
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unsigned long config);
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int (*to_irq)(struct gpio_chip *chip,
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unsigned offset);
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void (*dbg_show)(struct seq_file *s,
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struct gpio_chip *chip);
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int base;
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u16 ngpio;
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const char *const *names;
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bool can_sleep;
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#if IS_ENABLED(CONFIG_GPIO_GENERIC)
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unsigned long (*read_reg)(void __iomem *reg);
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void (*write_reg)(void __iomem *reg, unsigned long data);
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bool be_bits;
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void __iomem *reg_dat;
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void __iomem *reg_set;
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void __iomem *reg_clr;
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void __iomem *reg_dir;
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int bgpio_bits;
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spinlock_t bgpio_lock;
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unsigned long bgpio_data;
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unsigned long bgpio_dir;
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#endif
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#ifdef CONFIG_GPIOLIB_IRQCHIP
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/*
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* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
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* to handle IRQs for most practical cases.
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*/
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/**
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* @irq:
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*
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* Integrates interrupt chip functionality with the GPIO chip. Can be
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* used to handle IRQs for most practical cases.
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*/
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struct gpio_irq_chip irq;
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#endif
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/**
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* @need_valid_mask:
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*
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* If set core allocates @valid_mask with all bits set to one.
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*/
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bool need_valid_mask;
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/**
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* @valid_mask:
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*
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* If not %NULL holds bitmask of GPIOs which are valid to be used
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* from the chip.
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*/
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unsigned long *valid_mask;
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#if defined(CONFIG_OF_GPIO)
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/*
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* If CONFIG_OF is enabled, then all GPIO controllers described in the
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* device tree automatically may have an OF translation
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*/
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/**
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* @of_node:
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*
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* Pointer to a device tree node representing this GPIO controller.
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*/
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struct device_node *of_node;
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/**
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* @of_gpio_n_cells:
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*
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* Number of cells used to form the GPIO specifier.
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*/
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unsigned int of_gpio_n_cells;
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/**
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* @of_xlate:
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*
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* Callback to translate a device tree GPIO specifier into a chip-
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* relative GPIO number and flags.
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*/
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int (*of_xlate)(struct gpio_chip *gc,
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const struct of_phandle_args *gpiospec, u32 *flags);
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#endif
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};
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extern const char *gpiochip_is_requested(struct gpio_chip *chip,
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unsigned offset);
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/* add/remove chips */
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extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
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struct lock_class_key *lock_key,
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struct lock_class_key *request_key);
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/**
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* gpiochip_add_data() - register a gpio_chip
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* @chip: the chip to register, with chip->base initialized
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* @data: driver-private data associated with this chip
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*
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* Context: potentially before irqs will work
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*
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* When gpiochip_add_data() is called very early during boot, so that GPIOs
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* can be freely used, the chip->parent device must be registered before
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* the gpio framework's arch_initcall(). Otherwise sysfs initialization
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* for GPIOs will fail rudely.
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*
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* gpiochip_add_data() must only be called after gpiolib initialization,
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* ie after core_initcall().
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*
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* If chip->base is negative, this requests dynamic assignment of
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* a range of valid GPIOs.
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*
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* Returns:
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* A negative errno if the chip can't be registered, such as because the
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* chip->base is invalid or already associated with a different chip.
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* Otherwise it returns zero as a success code.
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*/
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#ifdef CONFIG_LOCKDEP
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#define gpiochip_add_data(chip, data) ({ \
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static struct lock_class_key lock_key; \
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static struct lock_class_key request_key; \
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gpiochip_add_data_with_key(chip, data, &lock_key, \
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&request_key); \
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})
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#else
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#define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL, NULL)
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#endif
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static inline int gpiochip_add(struct gpio_chip *chip)
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{
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return gpiochip_add_data(chip, NULL);
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}
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extern void gpiochip_remove(struct gpio_chip *chip);
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extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
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void *data);
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extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
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extern struct gpio_chip *gpiochip_find(void *data,
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int (*match)(struct gpio_chip *chip, void *data));
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/* lock/unlock as IRQ */
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int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
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void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
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bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
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/* Line status inquiry for drivers */
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bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
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bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
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/* Sleep persistence inquiry for drivers */
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bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
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bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset);
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/* get driver data */
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void *gpiochip_get_data(struct gpio_chip *chip);
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struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
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struct bgpio_pdata {
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const char *label;
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int base;
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int ngpio;
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};
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#if IS_ENABLED(CONFIG_GPIO_GENERIC)
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int bgpio_init(struct gpio_chip *gc, struct device *dev,
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unsigned long sz, void __iomem *dat, void __iomem *set,
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void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
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unsigned long flags);
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#define BGPIOF_BIG_ENDIAN BIT(0)
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#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
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#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
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#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
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#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
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#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
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#endif
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#ifdef CONFIG_GPIOLIB_IRQCHIP
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int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq);
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void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
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void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
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struct irq_chip *irqchip,
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unsigned int parent_irq,
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irq_flow_handler_t parent_handler);
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void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
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struct irq_chip *irqchip,
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unsigned int parent_irq);
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int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
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struct irq_chip *irqchip,
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unsigned int first_irq,
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irq_flow_handler_t handler,
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unsigned int type,
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bool threaded,
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struct lock_class_key *lock_key,
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struct lock_class_key *request_key);
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bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
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unsigned int offset);
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#ifdef CONFIG_LOCKDEP
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/*
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* Lockdep requires that each irqchip instance be created with a
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* unique key so as to avoid unnecessary warnings. This upfront
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* boilerplate static inlines provides such a key for each
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* unique instance.
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*/
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static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
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struct irq_chip *irqchip,
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unsigned int first_irq,
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irq_flow_handler_t handler,
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unsigned int type)
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{
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static struct lock_class_key lock_key;
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static struct lock_class_key request_key;
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return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
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handler, type, false,
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&lock_key, &request_key);
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}
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static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
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struct irq_chip *irqchip,
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unsigned int first_irq,
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irq_flow_handler_t handler,
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unsigned int type)
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{
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static struct lock_class_key lock_key;
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static struct lock_class_key request_key;
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return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
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handler, type, true,
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&lock_key, &request_key);
|
|
}
|
|
#else
|
|
static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
|
|
struct irq_chip *irqchip,
|
|
unsigned int first_irq,
|
|
irq_flow_handler_t handler,
|
|
unsigned int type)
|
|
{
|
|
return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
|
|
handler, type, false, NULL, NULL);
|
|
}
|
|
|
|
static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
|
|
struct irq_chip *irqchip,
|
|
unsigned int first_irq,
|
|
irq_flow_handler_t handler,
|
|
unsigned int type)
|
|
{
|
|
return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
|
|
handler, type, true, NULL, NULL);
|
|
}
|
|
#endif /* CONFIG_LOCKDEP */
|
|
|
|
#endif /* CONFIG_GPIOLIB_IRQCHIP */
|
|
|
|
int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
|
|
void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
|
|
int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
|
|
unsigned long config);
|
|
|
|
#ifdef CONFIG_PINCTRL
|
|
|
|
/**
|
|
* struct gpio_pin_range - pin range controlled by a gpio chip
|
|
* @node: list for maintaining set of pin ranges, used internally
|
|
* @pctldev: pinctrl device which handles corresponding pins
|
|
* @range: actual range of pins controlled by a gpio controller
|
|
*/
|
|
struct gpio_pin_range {
|
|
struct list_head node;
|
|
struct pinctrl_dev *pctldev;
|
|
struct pinctrl_gpio_range range;
|
|
};
|
|
|
|
int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
unsigned int npins);
|
|
int gpiochip_add_pingroup_range(struct gpio_chip *chip,
|
|
struct pinctrl_dev *pctldev,
|
|
unsigned int gpio_offset, const char *pin_group);
|
|
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
|
|
|
|
#else
|
|
|
|
static inline int
|
|
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
unsigned int npins)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int
|
|
gpiochip_add_pingroup_range(struct gpio_chip *chip,
|
|
struct pinctrl_dev *pctldev,
|
|
unsigned int gpio_offset, const char *pin_group)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void
|
|
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_PINCTRL */
|
|
|
|
struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
|
|
const char *label);
|
|
void gpiochip_free_own_desc(struct gpio_desc *desc);
|
|
|
|
#else /* CONFIG_GPIOLIB */
|
|
|
|
static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
|
|
{
|
|
/* GPIO can never have been requested */
|
|
WARN_ON(1);
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
#endif /* CONFIG_GPIOLIB */
|
|
|
|
#endif
|