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efc9b2048c
Commit2dc4940360("regulator: tps65218: Remove all the compatibles") changes the probe function of drivers/regulator/tps65218-regulator.c so that it iterates through all available regulators and assumes that the regulator IDs are sequential and match the order present in the enum tps65218_regulator_id. However, for some reason the much older commitc0ea88b890("regulator: tps65218: add support for LS3 current regulator") updated all arrays with LS3 at the end but added it second to last for the enum. Because of this long standing mismatch in order between the tps65218_regulator_id enum and the regulator_desc array in the tps65218 regulator driver, the new probe function causes the strobe values to be associated with the wrong regulator ID. This causes LDO1 to fail to suspend in tps65218_pmic_set_suspend_disable due to not having anything probes for its strobe value. Fix the order in the enum so the probe function works as the update intended. Fixes:2dc4940360("regulator: tps65218: Remove all the compatibles") Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
276 lines
7.8 KiB
C
276 lines
7.8 KiB
C
/*
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* linux/mfd/tps65218.h
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*
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* Functions to access TPS65219 power management chip.
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*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether expressed or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License version 2 for more details.
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*/
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#ifndef __LINUX_MFD_TPS65218_H
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#define __LINUX_MFD_TPS65218_H
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#include <linux/i2c.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/bitops.h>
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/* TPS chip id list */
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#define TPS65218 0xF0
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/* I2C ID for TPS65218 part */
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#define TPS65218_I2C_ID 0x24
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/* All register addresses */
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#define TPS65218_REG_CHIPID 0x00
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#define TPS65218_REG_INT1 0x01
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#define TPS65218_REG_INT2 0x02
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#define TPS65218_REG_INT_MASK1 0x03
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#define TPS65218_REG_INT_MASK2 0x04
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#define TPS65218_REG_STATUS 0x05
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#define TPS65218_REG_CONTROL 0x06
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#define TPS65218_REG_FLAG 0x07
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#define TPS65218_REG_PASSWORD 0x10
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#define TPS65218_REG_ENABLE1 0x11
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#define TPS65218_REG_ENABLE2 0x12
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#define TPS65218_REG_CONFIG1 0x13
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#define TPS65218_REG_CONFIG2 0x14
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#define TPS65218_REG_CONFIG3 0x15
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#define TPS65218_REG_CONTROL_DCDC1 0x16
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#define TPS65218_REG_CONTROL_DCDC2 0x17
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#define TPS65218_REG_CONTROL_DCDC3 0x18
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#define TPS65218_REG_CONTROL_DCDC4 0x19
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#define TPS65218_REG_CONTRL_SLEW_RATE 0x1A
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#define TPS65218_REG_CONTROL_LDO1 0x1B
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#define TPS65218_REG_SEQ1 0x20
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#define TPS65218_REG_SEQ2 0x21
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#define TPS65218_REG_SEQ3 0x22
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#define TPS65218_REG_SEQ4 0x23
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#define TPS65218_REG_SEQ5 0x24
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#define TPS65218_REG_SEQ6 0x25
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#define TPS65218_REG_SEQ7 0x26
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/* Register field definitions */
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#define TPS65218_CHIPID_CHIP_MASK 0xF8
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#define TPS65218_CHIPID_REV_MASK 0x07
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#define TPS65218_REV_1_0 0x0
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#define TPS65218_REV_1_1 0x1
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#define TPS65218_REV_2_0 0x2
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#define TPS65218_REV_2_1 0x3
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#define TPS65218_INT1_VPRG BIT(5)
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#define TPS65218_INT1_AC BIT(4)
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#define TPS65218_INT1_PB BIT(3)
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#define TPS65218_INT1_HOT BIT(2)
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#define TPS65218_INT1_CC_AQC BIT(1)
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#define TPS65218_INT1_PRGC BIT(0)
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#define TPS65218_INT2_LS3_F BIT(5)
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#define TPS65218_INT2_LS2_F BIT(4)
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#define TPS65218_INT2_LS1_F BIT(3)
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#define TPS65218_INT2_LS3_I BIT(2)
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#define TPS65218_INT2_LS2_I BIT(1)
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#define TPS65218_INT2_LS1_I BIT(0)
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#define TPS65218_INT_MASK1_VPRG BIT(5)
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#define TPS65218_INT_MASK1_AC BIT(4)
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#define TPS65218_INT_MASK1_PB BIT(3)
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#define TPS65218_INT_MASK1_HOT BIT(2)
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#define TPS65218_INT_MASK1_CC_AQC BIT(1)
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#define TPS65218_INT_MASK1_PRGC BIT(0)
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#define TPS65218_INT_MASK2_LS3_F BIT(5)
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#define TPS65218_INT_MASK2_LS2_F BIT(4)
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#define TPS65218_INT_MASK2_LS1_F BIT(3)
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#define TPS65218_INT_MASK2_LS3_I BIT(2)
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#define TPS65218_INT_MASK2_LS2_I BIT(1)
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#define TPS65218_INT_MASK2_LS1_I BIT(0)
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#define TPS65218_STATUS_FSEAL BIT(7)
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#define TPS65218_STATUS_EE BIT(6)
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#define TPS65218_STATUS_AC_STATE BIT(5)
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#define TPS65218_STATUS_PB_STATE BIT(4)
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#define TPS65218_STATUS_STATE_MASK 0xC
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#define TPS65218_STATUS_CC_STAT 0x3
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#define TPS65218_CONTROL_OFFNPFO BIT(1)
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#define TPS65218_CONTROL_CC_AQ BIT(0)
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#define TPS65218_FLAG_GPO3_FLG BIT(7)
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#define TPS65218_FLAG_GPO2_FLG BIT(6)
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#define TPS65218_FLAG_GPO1_FLG BIT(5)
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#define TPS65218_FLAG_LDO1_FLG BIT(4)
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#define TPS65218_FLAG_DC4_FLG BIT(3)
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#define TPS65218_FLAG_DC3_FLG BIT(2)
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#define TPS65218_FLAG_DC2_FLG BIT(1)
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#define TPS65218_FLAG_DC1_FLG BIT(0)
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#define TPS65218_ENABLE1_DC6_EN BIT(5)
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#define TPS65218_ENABLE1_DC5_EN BIT(4)
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#define TPS65218_ENABLE1_DC4_EN BIT(3)
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#define TPS65218_ENABLE1_DC3_EN BIT(2)
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#define TPS65218_ENABLE1_DC2_EN BIT(1)
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#define TPS65218_ENABLE1_DC1_EN BIT(0)
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#define TPS65218_ENABLE2_GPIO3 BIT(6)
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#define TPS65218_ENABLE2_GPIO2 BIT(5)
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#define TPS65218_ENABLE2_GPIO1 BIT(4)
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#define TPS65218_ENABLE2_LS3_EN BIT(3)
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#define TPS65218_ENABLE2_LS2_EN BIT(2)
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#define TPS65218_ENABLE2_LS1_EN BIT(1)
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#define TPS65218_ENABLE2_LDO1_EN BIT(0)
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#define TPS65218_CONFIG1_TRST BIT(7)
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#define TPS65218_CONFIG1_GPO2_BUF BIT(6)
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#define TPS65218_CONFIG1_IO1_SEL BIT(5)
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#define TPS65218_CONFIG1_PGDLY_MASK 0x18
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#define TPS65218_CONFIG1_STRICT BIT(2)
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#define TPS65218_CONFIG1_UVLO_MASK 0x3
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#define TPS65218_CONFIG2_DC12_RST BIT(7)
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#define TPS65218_CONFIG2_UVLOHYS BIT(6)
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#define TPS65218_CONFIG2_LS3ILIM_MASK 0xC
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#define TPS65218_CONFIG2_LS2ILIM_MASK 0x3
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#define TPS65218_CONFIG3_LS3NPFO BIT(5)
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#define TPS65218_CONFIG3_LS2NPFO BIT(4)
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#define TPS65218_CONFIG3_LS1NPFO BIT(3)
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#define TPS65218_CONFIG3_LS3DCHRG BIT(2)
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#define TPS65218_CONFIG3_LS2DCHRG BIT(1)
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#define TPS65218_CONFIG3_LS1DCHRG BIT(0)
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#define TPS65218_CONTROL_DCDC1_PFM BIT(7)
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#define TPS65218_CONTROL_DCDC1_MASK 0x7F
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#define TPS65218_CONTROL_DCDC2_PFM BIT(7)
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#define TPS65218_CONTROL_DCDC2_MASK 0x3F
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#define TPS65218_CONTROL_DCDC3_PFM BIT(7)
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#define TPS65218_CONTROL_DCDC3_MASK 0x3F
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#define TPS65218_CONTROL_DCDC4_PFM BIT(7)
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#define TPS65218_CONTROL_DCDC4_MASK 0x3F
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#define TPS65218_SLEW_RATE_GO BIT(7)
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#define TPS65218_SLEW_RATE_GODSBL BIT(6)
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#define TPS65218_SLEW_RATE_SLEW_MASK 0x7
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#define TPS65218_CONTROL_LDO1_MASK 0x3F
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#define TPS65218_SEQ1_DLY8 BIT(7)
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#define TPS65218_SEQ1_DLY7 BIT(6)
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#define TPS65218_SEQ1_DLY6 BIT(5)
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#define TPS65218_SEQ1_DLY5 BIT(4)
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#define TPS65218_SEQ1_DLY4 BIT(3)
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#define TPS65218_SEQ1_DLY3 BIT(2)
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#define TPS65218_SEQ1_DLY2 BIT(1)
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#define TPS65218_SEQ1_DLY1 BIT(0)
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#define TPS65218_SEQ2_DLYFCTR BIT(7)
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#define TPS65218_SEQ2_DLY9 BIT(0)
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#define TPS65218_SEQ3_DC2_SEQ_MASK 0xF0
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#define TPS65218_SEQ3_DC1_SEQ_MASK 0xF
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#define TPS65218_SEQ4_DC4_SEQ_MASK 0xF0
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#define TPS65218_SEQ4_DC3_SEQ_MASK 0xF
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#define TPS65218_SEQ5_DC6_SEQ_MASK 0xF0
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#define TPS65218_SEQ5_DC5_SEQ_MASK 0xF
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#define TPS65218_SEQ6_LS1_SEQ_MASK 0xF0
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#define TPS65218_SEQ6_LDO1_SEQ_MASK 0xF
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#define TPS65218_SEQ7_GPO3_SEQ_MASK 0xF0
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#define TPS65218_SEQ7_GPO1_SEQ_MASK 0xF
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#define TPS65218_PROTECT_NONE 0
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#define TPS65218_PROTECT_L1 1
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enum tps65218_regulator_id {
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/* DCDC's */
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TPS65218_DCDC_1,
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TPS65218_DCDC_2,
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TPS65218_DCDC_3,
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TPS65218_DCDC_4,
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TPS65218_DCDC_5,
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TPS65218_DCDC_6,
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/* LDOs */
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TPS65218_LDO_1,
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/* LS's */
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TPS65218_LS_3,
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};
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#define TPS65218_MAX_REG_ID TPS65218_LDO_1
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/* Number of step-down converters available */
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#define TPS65218_NUM_DCDC 6
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/* Number of LDO voltage regulators available */
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#define TPS65218_NUM_LDO 1
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/* Number of total LS current regulators available */
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#define TPS65218_NUM_LS 1
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/* Number of total regulators available */
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#define TPS65218_NUM_REGULATOR (TPS65218_NUM_DCDC + TPS65218_NUM_LDO \
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+ TPS65218_NUM_LS)
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/* Define the TPS65218 IRQ numbers */
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enum tps65218_irqs {
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/* INT1 registers */
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TPS65218_PRGC_IRQ,
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TPS65218_CC_AQC_IRQ,
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TPS65218_HOT_IRQ,
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TPS65218_PB_IRQ,
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TPS65218_AC_IRQ,
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TPS65218_VPRG_IRQ,
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TPS65218_INVALID1_IRQ,
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TPS65218_INVALID2_IRQ,
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/* INT2 registers */
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TPS65218_LS1_I_IRQ,
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TPS65218_LS2_I_IRQ,
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TPS65218_LS3_I_IRQ,
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TPS65218_LS1_F_IRQ,
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TPS65218_LS2_F_IRQ,
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TPS65218_LS3_F_IRQ,
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TPS65218_INVALID3_IRQ,
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TPS65218_INVALID4_IRQ,
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};
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/**
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* struct tps65218 - tps65218 sub-driver chip access routines
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*
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* Device data may be used to access the TPS65218 chip
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*/
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struct tps65218 {
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struct device *dev;
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unsigned int id;
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u8 rev;
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struct mutex tps_lock; /* lock guarding the data structure */
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/* IRQ Data */
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int irq;
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u32 irq_mask;
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struct regmap_irq_chip_data *irq_data;
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struct regulator_desc desc[TPS65218_NUM_REGULATOR];
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struct regmap *regmap;
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u8 *strobes;
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};
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int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
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unsigned int val, unsigned int level);
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int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
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unsigned int mask, unsigned int val, unsigned int level);
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int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
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unsigned int mask, unsigned int level);
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#endif /* __LINUX_MFD_TPS65218_H */
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