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1dd84d5e83
[ Upstream commit3185f96968] Add all the available resets for the video clock controller on sm8150. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-1-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> Stable-dep-of:1fd9a939db("clk: qcom: videocc-sm8150: Update the videocc resets") Signed-off-by: Sasha Levin <sashal@kernel.org>
29 lines
721 B
C
29 lines
721 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H
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#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H
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/* VIDEO_CC clocks */
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#define VIDEO_CC_IRIS_AHB_CLK 0
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#define VIDEO_CC_IRIS_CLK_SRC 1
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#define VIDEO_CC_MVS0_CORE_CLK 2
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#define VIDEO_CC_MVS1_CORE_CLK 3
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#define VIDEO_CC_MVSC_CORE_CLK 4
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#define VIDEO_CC_PLL0 5
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/* VIDEO_CC Resets */
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#define VIDEO_CC_MVSC_CORE_CLK_BCR 0
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#define VIDEO_CC_INTERFACE_BCR 1
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#define VIDEO_CC_MVS0_BCR 2
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#define VIDEO_CC_MVS1_BCR 3
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#define VIDEO_CC_MVSC_BCR 4
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/* VIDEO_CC GDSCRs */
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#define VENUS_GDSC 0
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#define VCODEC0_GDSC 1
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#define VCODEC1_GDSC 2
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#endif
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