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![Ioana Radulescu](/assets/img/avatar_default.png)
The DPAA2 Ethernet driver supports Freescale/NXP SoCs with DPAA2 (DataPath Acceleration Architecture v2). The driver manages network objects discovered on the fsl-mc bus. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
185 lines
8.1 KiB
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185 lines
8.1 KiB
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.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===============================
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DPAA2 Ethernet driver
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===============================
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:Copyright: |copy| 2017-2018 NXP
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This file provides documentation for the Freescale DPAA2 Ethernet driver.
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Supported Platforms
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===================
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This driver provides networking support for Freescale DPAA2 SoCs, e.g.
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LS2080A, LS2088A, LS1088A.
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Architecture Overview
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=====================
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Unlike regular NICs, in the DPAA2 architecture there is no single hardware block
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representing network interfaces; instead, several separate hardware resources
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concur to provide the networking functionality:
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- network interfaces
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- queues, channels
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- buffer pools
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- MAC/PHY
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All hardware resources are allocated and configured through the Management
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Complex (MC) portals. MC abstracts most of these resources as DPAA2 objects
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and exposes ABIs through which they can be configured and controlled. A few
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hardware resources, like queues, do not have a corresponding MC object and
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are treated as internal resources of other objects.
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For a more detailed description of the DPAA2 architecture and its object
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abstractions see *Documentation/networking/dpaa2/overview.rst*.
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Each Linux net device is built on top of a Datapath Network Interface (DPNI)
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object and uses Buffer Pools (DPBPs), I/O Portals (DPIOs) and Concentrators
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(DPCONs).
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Configuration interface::
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-----------------------
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| DPAA2 Ethernet Driver |
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-----------------------
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. . .
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. . .
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. . . . . . . . . . . .
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. . .
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. . .
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---------- ---------- -----------
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| DPBP API | | DPNI API | | DPCON API |
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---------- ---------- -----------
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. . . software
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======= . ========== . ============ . ===================
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. . . hardware
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------------------------------------------
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| MC hardware portals |
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------------------------------------------
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. . .
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. . .
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------ ------ -------
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| DPBP | | DPNI | | DPCON |
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------ ------ -------
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The DPNIs are network interfaces without a direct one-on-one mapping to PHYs.
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DPBPs represent hardware buffer pools. Packet I/O is performed in the context
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of DPCON objects, using DPIO portals for managing and communicating with the
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hardware resources.
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Datapath (I/O) interface::
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-----------------------------------------------
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| DPAA2 Ethernet Driver |
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-----------------------------------------------
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| ^ ^ | |
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| | | | |
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enqueue| dequeue| data | dequeue| seed |
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(Tx) | (Rx, TxC)| avail.| request| buffers|
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| | notify| | |
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V | | V V
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-----------------------------------------------
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| DPIO Driver |
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-----------------------------------------------
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| | | | | software
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| | | | | ================
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| | | | | hardware
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-----------------------------------------------
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| I/O hardware portals |
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-----------------------------------------------
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| ^ ^ | |
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| | | | |
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| | | V |
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V | ================ V
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---------------------- | -------------
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queues ---------------------- | | Buffer pool |
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---------------------- | -------------
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=======================
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Channel
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Datapath I/O (DPIO) portals provide enqueue and dequeue services, data
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availability notifications and buffer pool management. DPIOs are shared between
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all DPAA2 objects (and implicitly all DPAA2 kernel drivers) that work with data
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frames, but must be affine to the CPUs for the purpose of traffic distribution.
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Frames are transmitted and received through hardware frame queues, which can be
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grouped in channels for the purpose of hardware scheduling. The Ethernet driver
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enqueues TX frames on egress queues and after transmission is complete a TX
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confirmation frame is sent back to the CPU.
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When frames are available on ingress queues, a data availability notification
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is sent to the CPU; notifications are raised per channel, so even if multiple
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queues in the same channel have available frames, only one notification is sent.
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After a channel fires a notification, is must be explicitly rearmed.
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Each network interface can have multiple Rx, Tx and confirmation queues affined
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to CPUs, and one channel (DPCON) for each CPU that services at least one queue.
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DPCONs are used to distribute ingress traffic to different CPUs via the cores'
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affine DPIOs.
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The role of hardware buffer pools is storage of ingress frame data. Each network
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interface has a privately owned buffer pool which it seeds with kernel allocated
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buffers.
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DPNIs are decoupled from PHYs; a DPNI can be connected to a PHY through a DPMAC
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object or to another DPNI through an internal link, but the connection is
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managed by MC and completely transparent to the Ethernet driver.
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::
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--------- --------- ---------
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| eth if1 | | eth if2 | | eth ifn |
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--------- --------- ---------
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. . .
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. . .
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. . .
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---------------------------
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| DPAA2 Ethernet Driver |
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---------------------------
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. . .
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. . .
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. . .
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------ ------ ------ -------
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| DPNI | | DPNI | | DPNI | | DPMAC |----+
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------ ------ ------ ------- |
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| | | | |
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| | | | -----
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=========== ================== | PHY |
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-----
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Creating a Network Interface
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============================
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A net device is created for each DPNI object probed on the MC bus. Each DPNI has
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a number of properties which determine the network interface configuration
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options and associated hardware resources.
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DPNI objects (and the other DPAA2 objects needed for a network interface) can be
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added to a container on the MC bus in one of two ways: statically, through a
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Datapath Layout Binary file (DPL) that is parsed by MC at boot time; or created
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dynamically at runtime, via the DPAA2 objects APIs.
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Features & Offloads
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===================
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Hardware checksum offloading is supported for TCP and UDP over IPv4/6 frames.
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The checksum offloads can be independently configured on RX and TX through
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ethtool.
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Hardware offload of unicast and multicast MAC filtering is supported on the
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ingress path and permanently enabled.
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Scatter-gather frames are supported on both RX and TX paths. On TX, SG support
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is configurable via ethtool; on RX it is always enabled.
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The DPAA2 hardware can process jumbo Ethernet frames of up to 10K bytes.
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The Ethernet driver defines a static flow hashing scheme that distributes
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traffic based on a 5-tuple key: src IP, dst IP, IP proto, L4 src port,
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L4 dst port. No user configuration is supported for now.
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Hardware specific statistics for the network interface as well as some
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non-standard driver stats can be consulted through ethtool -S option.
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