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d09220a887
With the CMA changes from Joonsoo Kim <iamjoonsoo.kim@lge.com>, it was noticed that n900 stopped booting. After investigating it turned out that n900 save_secure_ram_context does some whacky virtual to physical address translation for the SRAM data address. As we now only have minimal parts of omap3 idle code copied to SRAM, running save_secure_ram_context() in SRAM is not needed. It only gets called on PM init. And it seems there's no need to ever call this from SRAM idle code. So let's just keep save_secure_ram_context() in DDR, and pass it the physical address of the parameters. We can do everything else in omap-secure.c like we already do for other secure code. And since we don't have any documentation, I still have no clue what the values for 0, 1 and 1 for the parameters might be. If somebody has figured it out, please do send a patch to add some comments. Debugged-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
/*
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* omap-secure.h: OMAP Secure infrastructure header.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
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* Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OMAP_ARCH_OMAP_SECURE_H
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#define OMAP_ARCH_OMAP_SECURE_H
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/* Monitor error code */
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#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
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#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
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/* HAL API error codes */
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#define API_HAL_RET_VALUE_OK 0x00
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#define API_HAL_RET_VALUE_FAIL 0x01
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/* Secure HAL API flags */
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#define FLAG_START_CRITICAL 0x4
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#define FLAG_IRQFIQ_MASK 0x3
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#define FLAG_IRQ_ENABLE 0x2
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#define FLAG_FIQ_ENABLE 0x1
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#define NO_FLAG 0x0
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/* Maximum Secure memory storage size */
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#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
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#define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
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/* Secure low power HAL API index */
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#define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a
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#define OMAP4_HAL_SAVEHW_INDEX 0x1b
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#define OMAP4_HAL_SAVEALL_INDEX 0x1c
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#define OMAP4_HAL_SAVEGIC_INDEX 0x1d
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/* Secure Monitor mode APIs */
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#define OMAP4_MON_SCU_PWR_INDEX 0x108
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#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
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#define OMAP4_MON_L2X0_CTRL_INDEX 0x102
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#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
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#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
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#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
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#define OMAP5_MON_AMBA_IF_INDEX 0x108
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#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
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/* Secure PPA(Primary Protected Application) APIs */
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#define OMAP4_PPA_L2_POR_INDEX 0x23
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#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
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/* Secure RX-51 PPA (Primary Protected Application) APIs */
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#define RX51_PPA_HWRNG 29
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#define RX51_PPA_L2_INVAL 40
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#define RX51_PPA_WRITE_ACR 42
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#ifndef __ASSEMBLER__
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extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
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extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
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extern phys_addr_t omap_secure_ram_mempool_base(void);
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extern int omap_secure_ram_reserve_memblock(void);
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extern u32 save_secure_ram_context(u32 args_pa);
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extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size);
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extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
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extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
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#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
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void set_cntfreq(void);
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#else
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static inline void set_cntfreq(void)
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{
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}
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#endif
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#endif /* __ASSEMBLER__ */
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#endif /* OMAP_ARCH_OMAP_SECURE_H */
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