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![Kelvin Cheung](/assets/img/avatar_default.png)
- Add clock lookups for APB devices. - Update clock relationship to make it more exact and clear. _____ _______________________| | OSC ___/ | MUX |___ XXX CLK \___ PLL ___ XXX DIV ___| | |_____| Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: mturquette@linaro.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8026/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
162 lines
4.9 KiB
C
162 lines
4.9 KiB
C
/*
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* Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <loongson1.h>
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#define OSC (33 * 1000000)
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#define DIV_APB 2
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static DEFINE_SPINLOCK(_lock);
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static int ls1x_pll_clk_enable(struct clk_hw *hw)
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{
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return 0;
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}
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static void ls1x_pll_clk_disable(struct clk_hw *hw)
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{
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}
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static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 pll, rate;
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pll = __raw_readl(LS1X_CLK_PLL_FREQ);
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rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
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rate *= OSC;
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rate >>= 1;
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return rate;
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}
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static const struct clk_ops ls1x_pll_clk_ops = {
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.enable = ls1x_pll_clk_enable,
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.disable = ls1x_pll_clk_disable,
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.recalc_rate = ls1x_pll_recalc_rate,
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};
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static struct clk *__init clk_register_pll(struct device *dev,
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const char *name,
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const char *parent_name,
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unsigned long flags)
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{
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struct clk_hw *hw;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the divider */
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hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
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if (!hw) {
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pr_err("%s: could not allocate clk_hw\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &ls1x_pll_clk_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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hw->init = &init;
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/* register the clock */
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clk = clk_register(dev, hw);
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if (IS_ERR(clk))
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kfree(hw);
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return clk;
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}
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static const char const *cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
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static const char const *ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };
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static const char const *dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
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void __init ls1x_clk_init(void)
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{
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struct clk *clk;
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clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, CLK_IS_ROOT,
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OSC);
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clk_register_clkdev(clk, "osc_33m_clk", NULL);
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/* clock derived from 33 MHz OSC clk */
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clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
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clk_register_clkdev(clk, "pll_clk", NULL);
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/* clock derived from PLL clk */
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/* _____
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* _______________________| |
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* OSC ___/ | MUX |___ CPU CLK
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* \___ PLL ___ CPU DIV ___| |
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* |_____|
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*/
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clk = clk_register_divider(NULL, "cpu_clk_div", "pll_clk",
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CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
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DIV_CPU_SHIFT, DIV_CPU_WIDTH,
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CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ROUND_CLOSEST, &_lock);
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clk_register_clkdev(clk, "cpu_clk_div", NULL);
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clk = clk_register_mux(NULL, "cpu_clk", cpu_parents,
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ARRAY_SIZE(cpu_parents),
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CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
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BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
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clk_register_clkdev(clk, "cpu_clk", NULL);
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/* _____
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* _______________________| |
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* OSC ___/ | MUX |___ DC CLK
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* \___ PLL ___ DC DIV ___| |
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* |_____|
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*/
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clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk",
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0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
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DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
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clk_register_clkdev(clk, "dc_clk_div", NULL);
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clk = clk_register_mux(NULL, "dc_clk", dc_parents,
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ARRAY_SIZE(dc_parents),
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CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
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BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
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clk_register_clkdev(clk, "dc_clk", NULL);
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/* _____
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* _______________________| |
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* OSC ___/ | MUX |___ DDR CLK
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* \___ PLL ___ DDR DIV ___| |
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* |_____|
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*/
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clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk",
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0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
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DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
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&_lock);
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clk_register_clkdev(clk, "ahb_clk_div", NULL);
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clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
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ARRAY_SIZE(ahb_parents),
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CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
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BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
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clk_register_clkdev(clk, "ahb_clk", NULL);
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clk_register_clkdev(clk, "stmmaceth", NULL);
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/* clock derived from AHB clk */
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/* APB clk is always half of the AHB clk */
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clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
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DIV_APB);
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clk_register_clkdev(clk, "apb_clk", NULL);
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clk_register_clkdev(clk, "ls1x_i2c", NULL);
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clk_register_clkdev(clk, "ls1x_pwmtimer", NULL);
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clk_register_clkdev(clk, "ls1x_spi", NULL);
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clk_register_clkdev(clk, "ls1x_wdt", NULL);
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clk_register_clkdev(clk, "serial8250", NULL);
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}
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