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![Javier Martinez Canillas](/assets/img/avatar_default.png)
Maxim Integrated Power Management ICs are very similar with regard to their clock outputs. Most of the clock drivers for these chips are duplicating code and are simpler enough that can be converted to use a generic driver to consolidate code and avoid duplication. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
192 lines
4.4 KiB
C
192 lines
4.4 KiB
C
/*
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* clk-max-gen.c - Generic clock driver for Maxim PMICs clocks
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*
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* Copyright (C) 2014 Google, Inc
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*
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* Copyright (C) 2012 Samsung Electornics
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* Jonghwa Lee <jonghwa3.lee@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This driver is based on clk-max77686.c
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*
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/regmap.h>
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/mutex.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/export.h>
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struct max_gen_clk {
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struct regmap *regmap;
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u32 mask;
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u32 reg;
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struct clk_hw hw;
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};
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static struct max_gen_clk *to_max_gen_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct max_gen_clk, hw);
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}
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static int max_gen_clk_prepare(struct clk_hw *hw)
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{
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struct max_gen_clk *max_gen = to_max_gen_clk(hw);
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return regmap_update_bits(max_gen->regmap, max_gen->reg,
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max_gen->mask, max_gen->mask);
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}
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static void max_gen_clk_unprepare(struct clk_hw *hw)
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{
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struct max_gen_clk *max_gen = to_max_gen_clk(hw);
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regmap_update_bits(max_gen->regmap, max_gen->reg,
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max_gen->mask, ~max_gen->mask);
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}
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static int max_gen_clk_is_prepared(struct clk_hw *hw)
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{
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struct max_gen_clk *max_gen = to_max_gen_clk(hw);
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int ret;
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u32 val;
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ret = regmap_read(max_gen->regmap, max_gen->reg, &val);
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if (ret < 0)
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return -EINVAL;
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return val & max_gen->mask;
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}
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static unsigned long max_gen_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return 32768;
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}
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struct clk_ops max_gen_clk_ops = {
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.prepare = max_gen_clk_prepare,
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.unprepare = max_gen_clk_unprepare,
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.is_prepared = max_gen_clk_is_prepared,
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.recalc_rate = max_gen_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(max_gen_clk_ops);
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static struct clk *max_gen_clk_register(struct device *dev,
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struct max_gen_clk *max_gen)
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{
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struct clk *clk;
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struct clk_hw *hw = &max_gen->hw;
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int ret;
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clk = devm_clk_register(dev, hw);
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if (IS_ERR(clk))
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return clk;
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ret = clk_register_clkdev(clk, hw->init->name, NULL);
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if (ret)
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return ERR_PTR(ret);
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return clk;
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}
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int max_gen_clk_probe(struct platform_device *pdev, struct regmap *regmap,
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u32 reg, struct clk_init_data *clks_init, int num_init)
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{
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int i, ret;
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struct max_gen_clk *max_gen_clks;
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struct clk **clocks;
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struct device *dev = pdev->dev.parent;
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const char *clk_name;
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struct clk_init_data *init;
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clocks = devm_kzalloc(dev, sizeof(struct clk *) * num_init, GFP_KERNEL);
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if (!clocks)
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return -ENOMEM;
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max_gen_clks = devm_kzalloc(dev, sizeof(struct max_gen_clk)
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* num_init, GFP_KERNEL);
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if (!max_gen_clks)
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return -ENOMEM;
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for (i = 0; i < num_init; i++) {
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max_gen_clks[i].regmap = regmap;
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max_gen_clks[i].mask = 1 << i;
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max_gen_clks[i].reg = reg;
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init = devm_kzalloc(dev, sizeof(*init), GFP_KERNEL);
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if (!init)
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return -ENOMEM;
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if (dev->of_node &&
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!of_property_read_string_index(dev->of_node,
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"clock-output-names",
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i, &clk_name))
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init->name = clk_name;
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else
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init->name = clks_init[i].name;
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init->ops = clks_init[i].ops;
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init->flags = clks_init[i].flags;
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max_gen_clks[i].hw.init = init;
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clocks[i] = max_gen_clk_register(dev, &max_gen_clks[i]);
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if (IS_ERR(clocks[i])) {
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ret = PTR_ERR(clocks[i]);
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dev_err(dev, "failed to register %s\n",
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max_gen_clks[i].hw.init->name);
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return ret;
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}
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}
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platform_set_drvdata(pdev, clocks);
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if (dev->of_node) {
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struct clk_onecell_data *of_data;
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of_data = devm_kzalloc(dev, sizeof(*of_data), GFP_KERNEL);
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if (!of_data)
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return -ENOMEM;
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of_data->clks = clocks;
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of_data->clk_num = num_init;
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ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
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of_data);
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if (ret) {
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dev_err(dev, "failed to register OF clock provider\n");
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return ret;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(max_gen_clk_probe);
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int max_gen_clk_remove(struct platform_device *pdev, int num_init)
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{
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struct device *dev = pdev->dev.parent;
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if (dev->of_node)
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of_clk_del_provider(dev->of_node);
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return 0;
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}
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EXPORT_SYMBOL_GPL(max_gen_clk_remove);
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