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much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUlMRQAAoJEDqPOy9afJhJgdUQAK4myJT0q10LSqe9piwzGVXg uDcIN5CTtbdYkvdGIfCjeqz3t+DClnAMPx2ZPIjC0Z1mIvqq+ViqwP5U8kKd7z1a WCKV8e5Et3O1WNbslzsx5Z2JYJNgzqr1xxWAOLTLh5rYxVwE5b946Yv4Whxa694I ugm4wNlibeN3H8pnyH8YEiWEtahtu7B5v/9WELpyREwNxw7ZA18MttEvWaamAPHG rAxhQCB3A3HaIvyg8KFdVmwOBZQMc2EWT00kJfdRWL4/iGAipKCnbuh1c8Pr/RQE XRg5Y+MuMLotoUELYYeZHtEmIlW3A+9gR6tLivswPpOP8/5BVUyA5Hh0yCGUqUHD s5Iheq7s7xnKEgIu9cD4tf1nCY41gw+4/I4pm47WLkaRgehcEBcAibVC3CupZ5pI hJiFqEKWPKEk8vAJ/mM+wCGI4w01+eoICBm4EG06Nwj4xkQcAVqE67ZvgVs1LrmL efqSxkWpNoetf0Q12cfePHmWtesGNdvljLdXQ54T4qH9HxNaI9/9eM6tyFTfrDSe BG5h7gbPr6/aM/1FfcWn5jQIfjEjPhQtSpCehs8pMf/pG5QZgftBtwe3p+yz7zXJ Q/v8xNEcZ7Ze6/9rJsAcbLzyzcdk9NzTlEMplzGBoUQFNiEXKoIjCDKAx39UFtMz EccWXvt9iNZZhmDcu0pU =jD84 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
335 lines
8 KiB
C
335 lines
8 KiB
C
/*
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* clk-s2mps11.c - Clock driver for S2MPS11.
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*
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* Copyright (C) 2013,2014 Samsung Electornics
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/clkdev.h>
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#include <linux/regmap.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/samsung/s2mps11.h>
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#include <linux/mfd/samsung/s2mps13.h>
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#include <linux/mfd/samsung/s2mps14.h>
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#include <linux/mfd/samsung/s5m8767.h>
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#include <linux/mfd/samsung/core.h>
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#define s2mps11_name(a) (a->hw.init->name)
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static struct clk **clk_table;
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static struct clk_onecell_data clk_data;
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enum {
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S2MPS11_CLK_AP = 0,
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S2MPS11_CLK_CP,
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S2MPS11_CLK_BT,
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S2MPS11_CLKS_NUM,
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};
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struct s2mps11_clk {
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struct sec_pmic_dev *iodev;
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struct device_node *clk_np;
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struct clk_hw hw;
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struct clk *clk;
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struct clk_lookup *lookup;
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u32 mask;
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unsigned int reg;
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};
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static struct s2mps11_clk *to_s2mps11_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct s2mps11_clk, hw);
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}
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static int s2mps11_clk_prepare(struct clk_hw *hw)
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{
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struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
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int ret;
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ret = regmap_update_bits(s2mps11->iodev->regmap_pmic,
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s2mps11->reg,
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s2mps11->mask, s2mps11->mask);
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return ret;
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}
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static void s2mps11_clk_unprepare(struct clk_hw *hw)
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{
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struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
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int ret;
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ret = regmap_update_bits(s2mps11->iodev->regmap_pmic, s2mps11->reg,
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s2mps11->mask, ~s2mps11->mask);
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}
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static int s2mps11_clk_is_prepared(struct clk_hw *hw)
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{
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int ret;
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u32 val;
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struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
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ret = regmap_read(s2mps11->iodev->regmap_pmic,
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s2mps11->reg, &val);
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if (ret < 0)
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return -EINVAL;
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return val & s2mps11->mask;
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}
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static unsigned long s2mps11_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return 32768;
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}
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static struct clk_ops s2mps11_clk_ops = {
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.prepare = s2mps11_clk_prepare,
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.unprepare = s2mps11_clk_unprepare,
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.is_prepared = s2mps11_clk_is_prepared,
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.recalc_rate = s2mps11_clk_recalc_rate,
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};
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static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
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[S2MPS11_CLK_AP] = {
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.name = "s2mps11_ap",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_CP] = {
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.name = "s2mps11_cp",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_BT] = {
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.name = "s2mps11_bt",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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};
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static struct clk_init_data s2mps13_clks_init[S2MPS11_CLKS_NUM] = {
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[S2MPS11_CLK_AP] = {
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.name = "s2mps13_ap",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_CP] = {
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.name = "s2mps13_cp",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_BT] = {
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.name = "s2mps13_bt",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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};
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static struct clk_init_data s2mps14_clks_init[S2MPS11_CLKS_NUM] = {
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[S2MPS11_CLK_AP] = {
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.name = "s2mps14_ap",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_BT] = {
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.name = "s2mps14_bt",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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};
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static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
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struct clk_init_data *clks_init)
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{
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struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
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struct device_node *clk_np;
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int i;
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if (!iodev->dev->of_node)
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return ERR_PTR(-EINVAL);
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clk_np = of_get_child_by_name(iodev->dev->of_node, "clocks");
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if (!clk_np) {
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dev_err(&pdev->dev, "could not find clock sub-node\n");
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return ERR_PTR(-EINVAL);
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}
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for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
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if (!clks_init[i].name)
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continue; /* Skip clocks not present in some devices */
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of_property_read_string_index(clk_np, "clock-output-names", i,
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&clks_init[i].name);
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}
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return clk_np;
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}
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static int s2mps11_clk_probe(struct platform_device *pdev)
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{
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struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
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struct s2mps11_clk *s2mps11_clks, *s2mps11_clk;
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unsigned int s2mps11_reg;
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struct clk_init_data *clks_init;
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int i, ret = 0;
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s2mps11_clks = devm_kzalloc(&pdev->dev, sizeof(*s2mps11_clk) *
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S2MPS11_CLKS_NUM, GFP_KERNEL);
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if (!s2mps11_clks)
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return -ENOMEM;
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s2mps11_clk = s2mps11_clks;
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clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk *) *
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S2MPS11_CLKS_NUM, GFP_KERNEL);
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if (!clk_table)
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return -ENOMEM;
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switch(platform_get_device_id(pdev)->driver_data) {
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case S2MPS11X:
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s2mps11_reg = S2MPS11_REG_RTC_CTRL;
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clks_init = s2mps11_clks_init;
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break;
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case S2MPS13X:
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s2mps11_reg = S2MPS13_REG_RTCCTRL;
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clks_init = s2mps13_clks_init;
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break;
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case S2MPS14X:
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s2mps11_reg = S2MPS14_REG_RTCCTRL;
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clks_init = s2mps14_clks_init;
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break;
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case S5M8767X:
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s2mps11_reg = S5M8767_REG_CTRL1;
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clks_init = s2mps11_clks_init;
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break;
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default:
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dev_err(&pdev->dev, "Invalid device type\n");
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return -EINVAL;
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}
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/* Store clocks of_node in first element of s2mps11_clks array */
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s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
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if (IS_ERR(s2mps11_clks->clk_np))
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return PTR_ERR(s2mps11_clks->clk_np);
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for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) {
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if (!clks_init[i].name)
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continue; /* Skip clocks not present in some devices */
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s2mps11_clk->iodev = iodev;
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s2mps11_clk->hw.init = &clks_init[i];
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s2mps11_clk->mask = 1 << i;
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s2mps11_clk->reg = s2mps11_reg;
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s2mps11_clk->clk = devm_clk_register(&pdev->dev,
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&s2mps11_clk->hw);
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if (IS_ERR(s2mps11_clk->clk)) {
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dev_err(&pdev->dev, "Fail to register : %s\n",
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s2mps11_name(s2mps11_clk));
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ret = PTR_ERR(s2mps11_clk->clk);
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goto err_reg;
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}
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s2mps11_clk->lookup = clkdev_alloc(s2mps11_clk->clk,
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s2mps11_name(s2mps11_clk), NULL);
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if (!s2mps11_clk->lookup) {
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ret = -ENOMEM;
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goto err_lup;
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}
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clkdev_add(s2mps11_clk->lookup);
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}
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for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
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/* Skip clocks not present on S2MPS14 */
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if (!clks_init[i].name)
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continue;
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clk_table[i] = s2mps11_clks[i].clk;
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}
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clk_data.clks = clk_table;
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clk_data.clk_num = S2MPS11_CLKS_NUM;
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of_clk_add_provider(s2mps11_clks->clk_np, of_clk_src_onecell_get,
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&clk_data);
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platform_set_drvdata(pdev, s2mps11_clks);
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return ret;
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err_lup:
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devm_clk_unregister(&pdev->dev, s2mps11_clk->clk);
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err_reg:
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while (s2mps11_clk > s2mps11_clks) {
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if (s2mps11_clk->lookup) {
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clkdev_drop(s2mps11_clk->lookup);
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devm_clk_unregister(&pdev->dev, s2mps11_clk->clk);
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}
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s2mps11_clk--;
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}
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return ret;
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}
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static int s2mps11_clk_remove(struct platform_device *pdev)
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{
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struct s2mps11_clk *s2mps11_clks = platform_get_drvdata(pdev);
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int i;
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of_clk_del_provider(s2mps11_clks[0].clk_np);
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/* Drop the reference obtained in s2mps11_clk_parse_dt */
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of_node_put(s2mps11_clks[0].clk_np);
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for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
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/* Skip clocks not present on S2MPS14 */
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if (!s2mps11_clks[i].lookup)
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continue;
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clkdev_drop(s2mps11_clks[i].lookup);
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}
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return 0;
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}
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static const struct platform_device_id s2mps11_clk_id[] = {
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{ "s2mps11-clk", S2MPS11X},
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{ "s2mps13-clk", S2MPS13X},
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{ "s2mps14-clk", S2MPS14X},
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{ "s5m8767-clk", S5M8767X},
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{ },
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};
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MODULE_DEVICE_TABLE(platform, s2mps11_clk_id);
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static struct platform_driver s2mps11_clk_driver = {
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.driver = {
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.name = "s2mps11-clk",
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},
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.probe = s2mps11_clk_probe,
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.remove = s2mps11_clk_remove,
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.id_table = s2mps11_clk_id,
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};
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static int __init s2mps11_clk_init(void)
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{
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return platform_driver_register(&s2mps11_clk_driver);
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}
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subsys_initcall(s2mps11_clk_init);
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static void __init s2mps11_clk_cleanup(void)
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{
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platform_driver_unregister(&s2mps11_clk_driver);
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}
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module_exit(s2mps11_clk_cleanup);
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MODULE_DESCRIPTION("S2MPS11 Clock Driver");
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MODULE_AUTHOR("Yadwinder Singh Brar <yadi.brar@samsung.com>");
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MODULE_LICENSE("GPL");
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