mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-21 10:01:00 +00:00
1a59d1b8e0
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
#ifndef __SOUND_PHASE_H
|
|
#define __SOUND_PHASE_H
|
|
|
|
/*
|
|
* ALSA driver for ICEnsemble ICE1712 (Envy24)
|
|
*
|
|
* Lowlevel functions for Terratec PHASE 22
|
|
*
|
|
* Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
|
|
*/
|
|
|
|
#define PHASE_DEVICE_DESC "{Terratec,Phase 22},"\
|
|
"{Terratec,Phase 28},"\
|
|
"{Terrasoniq,TS22},"
|
|
|
|
#define VT1724_SUBDEVICE_PHASE22 0x3b155011
|
|
#define VT1724_SUBDEVICE_PHASE28 0x3b154911
|
|
#define VT1724_SUBDEVICE_TS22 0x3b157b11
|
|
|
|
/* entry point */
|
|
extern struct snd_ice1712_card_info snd_vt1724_phase_cards[];
|
|
|
|
/* PHASE28 GPIO bits */
|
|
#define PHASE28_SPI_MISO (1 << 21)
|
|
#define PHASE28_WM_RESET (1 << 20)
|
|
#define PHASE28_SPI_CLK (1 << 19)
|
|
#define PHASE28_SPI_MOSI (1 << 18)
|
|
#define PHASE28_WM_RW (1 << 17)
|
|
#define PHASE28_AC97_RESET (1 << 16)
|
|
#define PHASE28_DIGITAL_SEL1 (1 << 15)
|
|
#define PHASE28_HP_SEL (1 << 14)
|
|
#define PHASE28_WM_CS (1 << 12)
|
|
#define PHASE28_AC97_COMMIT (1 << 11)
|
|
#define PHASE28_AC97_ADDR (1 << 10)
|
|
#define PHASE28_AC97_DATA_LOW (1 << 9)
|
|
#define PHASE28_AC97_DATA_HIGH (1 << 8)
|
|
#define PHASE28_AC97_DATA_MASK 0xFF
|
|
#endif /* __SOUND_PHASE */
|