100 lines
2.6 KiB
YAML
100 lines
2.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/thermal/mediatek,thermal.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek thermal controller for on-SoC temperatures
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maintainers:
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- Sascha Hauer <s.hauer@pengutronix.de>
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description:
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This device does not have its own ADC, instead it directly controls the AUXADC
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via AHB bus accesses. For this reason it needs phandles to the AUXADC. Also it
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controls a mux in the apmixedsys register space via AHB bus accesses, so a
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phandle to the APMIXEDSYS is also needed.
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allOf:
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- $ref: thermal-sensor.yaml#
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properties:
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compatible:
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enum:
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- mediatek,mt2701-thermal
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- mediatek,mt2712-thermal
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- mediatek,mt7622-thermal
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- mediatek,mt7981-thermal
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- mediatek,mt7986-thermal
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- mediatek,mt8173-thermal
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- mediatek,mt8183-thermal
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- mediatek,mt8365-thermal
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- mediatek,mt8516-thermal
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Main clock needed for register access
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- description: The AUXADC clock
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clock-names:
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items:
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- const: therm
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- const: auxadc
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mediatek,auxadc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to the AUXADC which the thermal controller uses
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mediatek,apmixedsys:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to the APMIXEDSYS controller
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resets:
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description: Reset controller controlling the thermal controller
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nvmem-cells:
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items:
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- description:
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NVMEM cell with EEPROMA phandle to the calibration data provided by an
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NVMEM device. If unspecified default values shall be used.
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nvmem-cell-names:
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items:
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- const: calibration-data
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required:
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- reg
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- interrupts
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- clocks
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- clock-names
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- mediatek,auxadc
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- mediatek,apmixedsys
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/reset/mt8173-resets.h>
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thermal@1100b000 {
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compatible = "mediatek,mt8173-thermal";
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reg = <0x1100b000 0x1000>;
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interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration_data>;
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nvmem-cell-names = "calibration-data";
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#thermal-sensor-cells = <1>;
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};
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