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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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c2bb705f45
Do not trust the fact that iio.h includes of.h which in turn includes all the headers we are relying on. The ultimate goal is to actually drop of.h from iio.h. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220610084545.547700-6-nuno.sa@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
495 lines
14 KiB
C
495 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* NXP i.MX8QXP ADC driver
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*
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* Based on the work of Haibo Chen <haibo.chen@nxp.com>
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* The initial developer of the original code is Haibo Chen.
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* Portions created by Haibo Chen are Copyright (C) 2018 NXP.
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* All Rights Reserved.
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*
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* Copyright (C) 2018 NXP
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* Copyright (C) 2021 Cai Huoqing
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/iio.h>
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#define ADC_DRIVER_NAME "imx8qxp-adc"
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/* Register map definition */
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#define IMX8QXP_ADR_ADC_CTRL 0x10
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#define IMX8QXP_ADR_ADC_STAT 0x14
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#define IMX8QXP_ADR_ADC_IE 0x18
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#define IMX8QXP_ADR_ADC_DE 0x1c
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#define IMX8QXP_ADR_ADC_CFG 0x20
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#define IMX8QXP_ADR_ADC_FCTRL 0x30
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#define IMX8QXP_ADR_ADC_SWTRIG 0x34
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#define IMX8QXP_ADR_ADC_TCTRL(tid) (0xc0 + (tid) * 4)
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#define IMX8QXP_ADR_ADC_CMDH(cid) (0x100 + (cid) * 8)
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#define IMX8QXP_ADR_ADC_CMDL(cid) (0x104 + (cid) * 8)
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#define IMX8QXP_ADR_ADC_RESFIFO 0x300
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#define IMX8QXP_ADR_ADC_TST 0xffc
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/* ADC bit shift */
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#define IMX8QXP_ADC_IE_FWMIE_MASK GENMASK(1, 0)
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#define IMX8QXP_ADC_CTRL_FIFO_RESET_MASK BIT(8)
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#define IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK BIT(1)
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#define IMX8QXP_ADC_CTRL_ADC_EN_MASK BIT(0)
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#define IMX8QXP_ADC_TCTRL_TCMD_MASK GENMASK(31, 24)
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#define IMX8QXP_ADC_TCTRL_TDLY_MASK GENMASK(23, 16)
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#define IMX8QXP_ADC_TCTRL_TPRI_MASK GENMASK(15, 8)
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#define IMX8QXP_ADC_TCTRL_HTEN_MASK GENMASK(7, 0)
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#define IMX8QXP_ADC_CMDL_CSCALE_MASK GENMASK(13, 8)
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#define IMX8QXP_ADC_CMDL_MODE_MASK BIT(7)
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#define IMX8QXP_ADC_CMDL_DIFF_MASK BIT(6)
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#define IMX8QXP_ADC_CMDL_ABSEL_MASK BIT(5)
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#define IMX8QXP_ADC_CMDL_ADCH_MASK GENMASK(2, 0)
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#define IMX8QXP_ADC_CMDH_NEXT_MASK GENMASK(31, 24)
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#define IMX8QXP_ADC_CMDH_LOOP_MASK GENMASK(23, 16)
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#define IMX8QXP_ADC_CMDH_AVGS_MASK GENMASK(15, 12)
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#define IMX8QXP_ADC_CMDH_STS_MASK BIT(8)
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#define IMX8QXP_ADC_CMDH_LWI_MASK GENMASK(7, 7)
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#define IMX8QXP_ADC_CMDH_CMPEN_MASK GENMASK(0, 0)
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#define IMX8QXP_ADC_CFG_PWREN_MASK BIT(28)
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#define IMX8QXP_ADC_CFG_PUDLY_MASK GENMASK(23, 16)
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#define IMX8QXP_ADC_CFG_REFSEL_MASK GENMASK(7, 6)
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#define IMX8QXP_ADC_CFG_PWRSEL_MASK GENMASK(5, 4)
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#define IMX8QXP_ADC_CFG_TPRICTRL_MASK GENMASK(3, 0)
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#define IMX8QXP_ADC_FCTRL_FWMARK_MASK GENMASK(20, 16)
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#define IMX8QXP_ADC_FCTRL_FCOUNT_MASK GENMASK(4, 0)
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#define IMX8QXP_ADC_RESFIFO_VAL_MASK GENMASK(18, 3)
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/* ADC PARAMETER*/
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#define IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL GENMASK(5, 0)
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#define IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL 0
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#define IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION 0
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#define IMX8QXP_ADC_CMDL_MODE_SINGLE 0
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#define IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS 0
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#define IMX8QXP_ADC_CMDH_CMPEN_DIS 0
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#define IMX8QXP_ADC_PAUSE_EN BIT(31)
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#define IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH 0
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#define IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS 0
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#define IMX8QXP_ADC_TIMEOUT msecs_to_jiffies(100)
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struct imx8qxp_adc {
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struct device *dev;
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void __iomem *regs;
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struct clk *clk;
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struct clk *ipg_clk;
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struct regulator *vref;
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/* Serialise ADC channel reads */
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struct mutex lock;
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struct completion completion;
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};
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#define IMX8QXP_ADC_CHAN(_idx) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (_idx), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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}
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static const struct iio_chan_spec imx8qxp_adc_iio_channels[] = {
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IMX8QXP_ADC_CHAN(0),
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IMX8QXP_ADC_CHAN(1),
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IMX8QXP_ADC_CHAN(2),
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IMX8QXP_ADC_CHAN(3),
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IMX8QXP_ADC_CHAN(4),
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IMX8QXP_ADC_CHAN(5),
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IMX8QXP_ADC_CHAN(6),
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IMX8QXP_ADC_CHAN(7),
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};
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static void imx8qxp_adc_reset(struct imx8qxp_adc *adc)
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{
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u32 ctrl;
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/*software reset, need to clear the set bit*/
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ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
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ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
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writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
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udelay(10);
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ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
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writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
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/* reset the fifo */
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ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_FIFO_RESET_MASK, 1);
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writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
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}
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static void imx8qxp_adc_reg_config(struct imx8qxp_adc *adc, int channel)
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{
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u32 adc_cfg, adc_tctrl, adc_cmdl, adc_cmdh;
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/* ADC configuration */
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adc_cfg = FIELD_PREP(IMX8QXP_ADC_CFG_PWREN_MASK, 1) |
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FIELD_PREP(IMX8QXP_ADC_CFG_PUDLY_MASK, 0x80)|
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FIELD_PREP(IMX8QXP_ADC_CFG_REFSEL_MASK, 0) |
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FIELD_PREP(IMX8QXP_ADC_CFG_PWRSEL_MASK, 3) |
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FIELD_PREP(IMX8QXP_ADC_CFG_TPRICTRL_MASK, 0);
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writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG);
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/* config the trigger control */
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adc_tctrl = FIELD_PREP(IMX8QXP_ADC_TCTRL_TCMD_MASK, 1) |
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FIELD_PREP(IMX8QXP_ADC_TCTRL_TDLY_MASK, 0) |
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FIELD_PREP(IMX8QXP_ADC_TCTRL_TPRI_MASK, IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH) |
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FIELD_PREP(IMX8QXP_ADC_TCTRL_HTEN_MASK, IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS);
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writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0));
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/* config the cmd */
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adc_cmdl = FIELD_PREP(IMX8QXP_ADC_CMDL_CSCALE_MASK, IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL) |
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FIELD_PREP(IMX8QXP_ADC_CMDL_MODE_MASK, IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION) |
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FIELD_PREP(IMX8QXP_ADC_CMDL_DIFF_MASK, IMX8QXP_ADC_CMDL_MODE_SINGLE) |
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FIELD_PREP(IMX8QXP_ADC_CMDL_ABSEL_MASK, IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL) |
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FIELD_PREP(IMX8QXP_ADC_CMDL_ADCH_MASK, channel);
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writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0));
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adc_cmdh = FIELD_PREP(IMX8QXP_ADC_CMDH_NEXT_MASK, 0) |
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FIELD_PREP(IMX8QXP_ADC_CMDH_LOOP_MASK, 0) |
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FIELD_PREP(IMX8QXP_ADC_CMDH_AVGS_MASK, 7) |
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FIELD_PREP(IMX8QXP_ADC_CMDH_STS_MASK, 0) |
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FIELD_PREP(IMX8QXP_ADC_CMDH_LWI_MASK, IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS) |
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FIELD_PREP(IMX8QXP_ADC_CMDH_CMPEN_MASK, IMX8QXP_ADC_CMDH_CMPEN_DIS);
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writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0));
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}
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static void imx8qxp_adc_fifo_config(struct imx8qxp_adc *adc)
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{
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u32 fifo_ctrl, interrupt_en;
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fifo_ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL);
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fifo_ctrl &= ~IMX8QXP_ADC_FCTRL_FWMARK_MASK;
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/* set the watermark level to 1 */
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fifo_ctrl |= FIELD_PREP(IMX8QXP_ADC_FCTRL_FWMARK_MASK, 0);
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writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL);
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/* FIFO Watermark Interrupt Enable */
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interrupt_en = readl(adc->regs + IMX8QXP_ADR_ADC_IE);
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interrupt_en |= FIELD_PREP(IMX8QXP_ADC_IE_FWMIE_MASK, 1);
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writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE);
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}
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static void imx8qxp_adc_disable(struct imx8qxp_adc *adc)
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{
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u32 ctrl;
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ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
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ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
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writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
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}
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static int imx8qxp_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct imx8qxp_adc *adc = iio_priv(indio_dev);
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struct device *dev = adc->dev;
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u32 ctrl, vref_uv;
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long ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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pm_runtime_get_sync(dev);
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mutex_lock(&adc->lock);
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reinit_completion(&adc->completion);
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imx8qxp_adc_reg_config(adc, chan->channel);
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imx8qxp_adc_fifo_config(adc);
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/* adc enable */
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ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
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ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
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writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
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/* adc start */
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writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG);
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ret = wait_for_completion_interruptible_timeout(&adc->completion,
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IMX8QXP_ADC_TIMEOUT);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_sync_autosuspend(dev);
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if (ret == 0) {
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mutex_unlock(&adc->lock);
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return -ETIMEDOUT;
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}
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if (ret < 0) {
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mutex_unlock(&adc->lock);
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return ret;
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}
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*val = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
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readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
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mutex_unlock(&adc->lock);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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vref_uv = regulator_get_voltage(adc->vref);
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*val = vref_uv / 1000;
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*val2 = 12;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = clk_get_rate(adc->clk) / 3;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id)
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{
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struct imx8qxp_adc *adc = dev_id;
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u32 fifo_count;
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fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK,
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readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
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if (fifo_count)
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complete(&adc->completion);
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return IRQ_HANDLED;
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}
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static int imx8qxp_adc_reg_access(struct iio_dev *indio_dev, unsigned int reg,
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unsigned int writeval, unsigned int *readval)
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{
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struct imx8qxp_adc *adc = iio_priv(indio_dev);
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struct device *dev = adc->dev;
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if (!readval || reg % 4 || reg > IMX8QXP_ADR_ADC_TST)
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return -EINVAL;
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pm_runtime_get_sync(dev);
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*readval = readl(adc->regs + reg);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_sync_autosuspend(dev);
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return 0;
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}
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static const struct iio_info imx8qxp_adc_iio_info = {
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.read_raw = &imx8qxp_adc_read_raw,
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.debugfs_reg_access = &imx8qxp_adc_reg_access,
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};
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static int imx8qxp_adc_probe(struct platform_device *pdev)
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{
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struct imx8qxp_adc *adc;
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struct iio_dev *indio_dev;
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struct device *dev = &pdev->dev;
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int irq;
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int ret;
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indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
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if (!indio_dev) {
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dev_err(dev, "Failed allocating iio device\n");
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return -ENOMEM;
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}
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adc = iio_priv(indio_dev);
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adc->dev = dev;
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mutex_init(&adc->lock);
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adc->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(adc->regs))
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return PTR_ERR(adc->regs);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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adc->clk = devm_clk_get(dev, "per");
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if (IS_ERR(adc->clk))
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return dev_err_probe(dev, PTR_ERR(adc->clk), "Failed getting clock\n");
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adc->ipg_clk = devm_clk_get(dev, "ipg");
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if (IS_ERR(adc->ipg_clk))
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return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), "Failed getting clock\n");
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adc->vref = devm_regulator_get(dev, "vref");
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if (IS_ERR(adc->vref))
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return dev_err_probe(dev, PTR_ERR(adc->vref), "Failed getting reference voltage\n");
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ret = regulator_enable(adc->vref);
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if (ret) {
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dev_err(dev, "Can't enable adc reference top voltage\n");
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return ret;
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}
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platform_set_drvdata(pdev, indio_dev);
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init_completion(&adc->completion);
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indio_dev->name = ADC_DRIVER_NAME;
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indio_dev->info = &imx8qxp_adc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = imx8qxp_adc_iio_channels;
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indio_dev->num_channels = ARRAY_SIZE(imx8qxp_adc_iio_channels);
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ret = clk_prepare_enable(adc->clk);
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if (ret) {
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dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
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goto error_regulator_disable;
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}
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ret = clk_prepare_enable(adc->ipg_clk);
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if (ret) {
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dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
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goto error_adc_clk_disable;
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}
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ret = devm_request_irq(dev, irq, imx8qxp_adc_isr, 0, ADC_DRIVER_NAME, adc);
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if (ret < 0) {
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dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
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goto error_ipg_clk_disable;
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}
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imx8qxp_adc_reset(adc);
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ret = iio_device_register(indio_dev);
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if (ret) {
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imx8qxp_adc_disable(adc);
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dev_err(dev, "Couldn't register the device.\n");
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goto error_ipg_clk_disable;
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}
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pm_runtime_set_active(dev);
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pm_runtime_set_autosuspend_delay(dev, 50);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_enable(dev);
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return 0;
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error_ipg_clk_disable:
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clk_disable_unprepare(adc->ipg_clk);
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error_adc_clk_disable:
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clk_disable_unprepare(adc->clk);
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error_regulator_disable:
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regulator_disable(adc->vref);
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return ret;
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}
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static int imx8qxp_adc_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct imx8qxp_adc *adc = iio_priv(indio_dev);
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struct device *dev = adc->dev;
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pm_runtime_get_sync(dev);
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iio_device_unregister(indio_dev);
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imx8qxp_adc_disable(adc);
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clk_disable_unprepare(adc->clk);
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clk_disable_unprepare(adc->ipg_clk);
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regulator_disable(adc->vref);
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pm_runtime_disable(dev);
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pm_runtime_put_noidle(dev);
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return 0;
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}
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static __maybe_unused int imx8qxp_adc_runtime_suspend(struct device *dev)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct imx8qxp_adc *adc = iio_priv(indio_dev);
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imx8qxp_adc_disable(adc);
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clk_disable_unprepare(adc->clk);
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clk_disable_unprepare(adc->ipg_clk);
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regulator_disable(adc->vref);
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return 0;
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}
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static __maybe_unused int imx8qxp_adc_runtime_resume(struct device *dev)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct imx8qxp_adc *adc = iio_priv(indio_dev);
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int ret;
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ret = regulator_enable(adc->vref);
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if (ret) {
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dev_err(dev, "Can't enable adc reference top voltage, err = %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(adc->clk);
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if (ret) {
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dev_err(dev, "Could not prepare or enable clock.\n");
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goto err_disable_reg;
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}
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ret = clk_prepare_enable(adc->ipg_clk);
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if (ret) {
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dev_err(dev, "Could not prepare or enable clock.\n");
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goto err_unprepare_clk;
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}
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imx8qxp_adc_reset(adc);
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return 0;
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err_unprepare_clk:
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clk_disable_unprepare(adc->clk);
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err_disable_reg:
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regulator_disable(adc->vref);
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return ret;
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}
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static const struct dev_pm_ops imx8qxp_adc_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(imx8qxp_adc_runtime_suspend, imx8qxp_adc_runtime_resume, NULL)
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};
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static const struct of_device_id imx8qxp_adc_match[] = {
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{ .compatible = "nxp,imx8qxp-adc", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx8qxp_adc_match);
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static struct platform_driver imx8qxp_adc_driver = {
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.probe = imx8qxp_adc_probe,
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.remove = imx8qxp_adc_remove,
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.driver = {
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.name = ADC_DRIVER_NAME,
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.of_match_table = imx8qxp_adc_match,
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.pm = &imx8qxp_adc_pm_ops,
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},
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};
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module_platform_driver(imx8qxp_adc_driver);
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MODULE_DESCRIPTION("i.MX8QuadXPlus ADC driver");
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MODULE_LICENSE("GPL v2");
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