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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 53 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.904365654@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
441 lines
11 KiB
C
441 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip PCIe PHY driver
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*
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* Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
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* Copyright (C) 2016 ROCKCHIP, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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/*
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* The higher 16-bit of this register is used for write protection
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* only if BIT(x + 16) set to 1 the BIT(x) can be written.
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*/
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define PHY_MAX_LANE_NUM 4
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#define PHY_CFG_DATA_SHIFT 7
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#define PHY_CFG_ADDR_SHIFT 1
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#define PHY_CFG_DATA_MASK 0xf
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#define PHY_CFG_ADDR_MASK 0x3f
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#define PHY_CFG_RD_MASK 0x3ff
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#define PHY_CFG_WR_ENABLE 1
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#define PHY_CFG_WR_DISABLE 1
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#define PHY_CFG_WR_SHIFT 0
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#define PHY_CFG_WR_MASK 1
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#define PHY_CFG_PLL_LOCK 0x10
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#define PHY_CFG_CLK_TEST 0x10
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#define PHY_CFG_CLK_SCC 0x12
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#define PHY_CFG_SEPE_RATE BIT(3)
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#define PHY_CFG_PLL_100M BIT(3)
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#define PHY_PLL_LOCKED BIT(9)
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#define PHY_PLL_OUTPUT BIT(10)
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#define PHY_LANE_A_STATUS 0x30
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#define PHY_LANE_B_STATUS 0x31
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#define PHY_LANE_C_STATUS 0x32
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#define PHY_LANE_D_STATUS 0x33
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#define PHY_LANE_RX_DET_SHIFT 11
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#define PHY_LANE_RX_DET_TH 0x1
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#define PHY_LANE_IDLE_OFF 0x1
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#define PHY_LANE_IDLE_MASK 0x1
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#define PHY_LANE_IDLE_A_SHIFT 3
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#define PHY_LANE_IDLE_B_SHIFT 4
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#define PHY_LANE_IDLE_C_SHIFT 5
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#define PHY_LANE_IDLE_D_SHIFT 6
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struct rockchip_pcie_data {
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unsigned int pcie_conf;
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unsigned int pcie_status;
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unsigned int pcie_laneoff;
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};
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struct rockchip_pcie_phy {
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struct rockchip_pcie_data *phy_data;
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struct regmap *reg_base;
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struct phy_pcie_instance {
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struct phy *phy;
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u32 index;
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} phys[PHY_MAX_LANE_NUM];
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struct mutex pcie_mutex;
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struct reset_control *phy_rst;
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struct clk *clk_pciephy_ref;
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int pwr_cnt;
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int init_cnt;
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};
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static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
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{
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return container_of(inst, struct rockchip_pcie_phy,
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phys[inst->index]);
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}
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static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
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if (args->args_count == 0)
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return rk_phy->phys[0].phy;
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if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
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return ERR_PTR(-ENODEV);
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return rk_phy->phys[args->args[0]].phy;
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}
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static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
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u32 addr, u32 data)
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{
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regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
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HIWORD_UPDATE(data,
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PHY_CFG_DATA_MASK,
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PHY_CFG_DATA_SHIFT) |
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HIWORD_UPDATE(addr,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT));
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udelay(1);
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regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
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HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT));
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udelay(1);
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regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
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HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT));
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}
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static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
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u32 addr)
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{
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u32 val;
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regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
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HIWORD_UPDATE(addr,
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PHY_CFG_RD_MASK,
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PHY_CFG_ADDR_SHIFT));
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regmap_read(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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&val);
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return val;
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}
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static int rockchip_pcie_phy_power_off(struct phy *phy)
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{
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struct phy_pcie_instance *inst = phy_get_drvdata(phy);
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struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
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int err = 0;
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mutex_lock(&rk_phy->pcie_mutex);
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regmap_write(rk_phy->reg_base,
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rk_phy->phy_data->pcie_laneoff,
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HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT + inst->index));
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if (--rk_phy->pwr_cnt)
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goto err_out;
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err = reset_control_assert(rk_phy->phy_rst);
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if (err) {
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dev_err(&phy->dev, "assert phy_rst err %d\n", err);
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goto err_restore;
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}
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err_out:
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mutex_unlock(&rk_phy->pcie_mutex);
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return 0;
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err_restore:
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rk_phy->pwr_cnt++;
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regmap_write(rk_phy->reg_base,
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rk_phy->phy_data->pcie_laneoff,
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HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT + inst->index));
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mutex_unlock(&rk_phy->pcie_mutex);
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return err;
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}
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static int rockchip_pcie_phy_power_on(struct phy *phy)
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{
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struct phy_pcie_instance *inst = phy_get_drvdata(phy);
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struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
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int err = 0;
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u32 status;
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unsigned long timeout;
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mutex_lock(&rk_phy->pcie_mutex);
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if (rk_phy->pwr_cnt++)
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goto err_out;
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err = reset_control_deassert(rk_phy->phy_rst);
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if (err) {
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dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
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goto err_pwr_cnt;
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}
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regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
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HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT));
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regmap_write(rk_phy->reg_base,
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rk_phy->phy_data->pcie_laneoff,
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HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT + inst->index));
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/*
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* No documented timeout value for phy operation below,
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* so we make it large enough here. And we use loop-break
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* method which should not be harmful.
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*/
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timeout = jiffies + msecs_to_jiffies(1000);
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err = -EINVAL;
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while (time_before(jiffies, timeout)) {
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regmap_read(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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&status);
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if (status & PHY_PLL_LOCKED) {
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dev_dbg(&phy->dev, "pll locked!\n");
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err = 0;
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break;
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}
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msleep(20);
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}
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if (err) {
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dev_err(&phy->dev, "pll lock timeout!\n");
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goto err_pll_lock;
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}
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phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
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phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
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err = -ETIMEDOUT;
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while (time_before(jiffies, timeout)) {
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regmap_read(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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&status);
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if (!(status & PHY_PLL_OUTPUT)) {
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dev_dbg(&phy->dev, "pll output enable done!\n");
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err = 0;
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break;
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}
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msleep(20);
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}
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if (err) {
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dev_err(&phy->dev, "pll output enable timeout!\n");
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goto err_pll_lock;
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}
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regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
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HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT));
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err = -EINVAL;
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while (time_before(jiffies, timeout)) {
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regmap_read(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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&status);
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if (status & PHY_PLL_LOCKED) {
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dev_dbg(&phy->dev, "pll relocked!\n");
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err = 0;
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break;
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}
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msleep(20);
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}
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if (err) {
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dev_err(&phy->dev, "pll relock timeout!\n");
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goto err_pll_lock;
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}
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err_out:
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mutex_unlock(&rk_phy->pcie_mutex);
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return 0;
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err_pll_lock:
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reset_control_assert(rk_phy->phy_rst);
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err_pwr_cnt:
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rk_phy->pwr_cnt--;
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mutex_unlock(&rk_phy->pcie_mutex);
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return err;
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}
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static int rockchip_pcie_phy_init(struct phy *phy)
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{
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struct phy_pcie_instance *inst = phy_get_drvdata(phy);
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struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
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int err = 0;
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mutex_lock(&rk_phy->pcie_mutex);
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if (rk_phy->init_cnt++)
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goto err_out;
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err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
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if (err) {
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dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
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goto err_refclk;
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}
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err = reset_control_assert(rk_phy->phy_rst);
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if (err) {
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dev_err(&phy->dev, "assert phy_rst err %d\n", err);
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goto err_reset;
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}
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err_out:
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mutex_unlock(&rk_phy->pcie_mutex);
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return 0;
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err_reset:
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clk_disable_unprepare(rk_phy->clk_pciephy_ref);
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err_refclk:
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rk_phy->init_cnt--;
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mutex_unlock(&rk_phy->pcie_mutex);
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return err;
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}
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static int rockchip_pcie_phy_exit(struct phy *phy)
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{
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struct phy_pcie_instance *inst = phy_get_drvdata(phy);
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struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
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mutex_lock(&rk_phy->pcie_mutex);
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if (--rk_phy->init_cnt)
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goto err_init_cnt;
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clk_disable_unprepare(rk_phy->clk_pciephy_ref);
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err_init_cnt:
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mutex_unlock(&rk_phy->pcie_mutex);
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return 0;
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}
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static const struct phy_ops ops = {
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.init = rockchip_pcie_phy_init,
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.exit = rockchip_pcie_phy_exit,
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.power_on = rockchip_pcie_phy_power_on,
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.power_off = rockchip_pcie_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct rockchip_pcie_data rk3399_pcie_data = {
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.pcie_conf = 0xe220,
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.pcie_status = 0xe2a4,
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.pcie_laneoff = 0xe214,
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};
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static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
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{
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.compatible = "rockchip,rk3399-pcie-phy",
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.data = &rk3399_pcie_data,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
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static int rockchip_pcie_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rockchip_pcie_phy *rk_phy;
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struct phy_provider *phy_provider;
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struct regmap *grf;
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const struct of_device_id *of_id;
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int i;
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u32 phy_num;
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grf = syscon_node_to_regmap(dev->parent->of_node);
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if (IS_ERR(grf)) {
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dev_err(dev, "Cannot find GRF syscon\n");
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return PTR_ERR(grf);
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}
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rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
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if (!rk_phy)
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return -ENOMEM;
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of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev);
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if (!of_id)
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return -EINVAL;
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rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
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rk_phy->reg_base = grf;
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mutex_init(&rk_phy->pcie_mutex);
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rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
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if (IS_ERR(rk_phy->phy_rst)) {
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if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
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dev_err(dev,
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"missing phy property for reset controller\n");
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return PTR_ERR(rk_phy->phy_rst);
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}
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rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
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if (IS_ERR(rk_phy->clk_pciephy_ref)) {
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dev_err(dev, "refclk not found.\n");
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return PTR_ERR(rk_phy->clk_pciephy_ref);
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}
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/* parse #phy-cells to see if it's legacy PHY model */
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if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
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return -ENOENT;
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phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
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dev_dbg(dev, "phy number is %d\n", phy_num);
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for (i = 0; i < phy_num; i++) {
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rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
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if (IS_ERR(rk_phy->phys[i].phy)) {
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dev_err(dev, "failed to create PHY%d\n", i);
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return PTR_ERR(rk_phy->phys[i].phy);
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}
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rk_phy->phys[i].index = i;
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phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
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}
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platform_set_drvdata(pdev, rk_phy);
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phy_provider = devm_of_phy_provider_register(dev,
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rockchip_pcie_phy_of_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver rockchip_pcie_driver = {
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.probe = rockchip_pcie_phy_probe,
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.driver = {
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.name = "rockchip-pcie-phy",
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.of_match_table = rockchip_pcie_phy_dt_ids,
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},
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};
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module_platform_driver(rockchip_pcie_driver);
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MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
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MODULE_LICENSE("GPL v2");
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