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8a01032e02
In the start of the "vnt_rf_set_txpower" function the "power" variable
is set at most to VNT_RF_MAX_POWER (hex = 0x3f, dec = 63). Then, in the
switch statement there are four comparisons with the "power" variable
against AL7230_PWR_IDX_LEN (dec = 64), VT3226_PWR_IDX_LEN (dec = 64),
VT3342_PWR_IDX_LEN (dec = 64). Due to all the commented comparisons are
to check if the "power" variable is "greater than or equal" to 64, this
never happens. So, remove the logically dead code.
Also, remove all the defines that are no longer required.
Addresses-Coverity-ID: 1230228 ("Logically dead code")
Fixes: f53d9f12c5 ("staging: vt6656: rf.c additional power.")
Signed-off-by: Oscar Carter <oscar.carter@gmx.com>
Link: https://lore.kernel.org/r/20200510090950.7633-1-oscar.carter@gmx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
855 lines
18 KiB
C
855 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
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* All rights reserved.
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*
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* File: rf.c
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*
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* Purpose: rf function code
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*
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* Author: Jerry Chen
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*
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* Date: Feb. 19, 2004
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*
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* Functions:
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* vnt_rf_write_embedded - Embedded write RF register via MAC
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*
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* Revision History:
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* RF_VT3226: RobertYu:20051111, VT3226C0 and before
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* RF_VT3226D0: RobertYu:20051228
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* RF_VT3342A0: RobertYu:20060609
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*
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*/
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#include <linux/errno.h>
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#include "mac.h"
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#include "rf.h"
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#include "baseband.h"
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#include "usbpipe.h"
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#define CB_AL2230_INIT_SEQ 15
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#define CB_AL7230_INIT_SEQ 16
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#define CB_VT3226_INIT_SEQ 11
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#define CB_VT3342_INIT_SEQ 13
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static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = {
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{0x03, 0xf7, 0x90},
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{0x03, 0x33, 0x31},
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{0x01, 0xb8, 0x02},
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{0x00, 0xff, 0xf3},
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{0x00, 0x05, 0xa4},
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{0x0f, 0x4d, 0xc5},
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{0x08, 0x05, 0xb6},
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{0x01, 0x47, 0xc7},
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{0x00, 0x06, 0x88},
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{0x04, 0x03, 0xb9},
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{0x00, 0xdb, 0xba},
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{0x00, 0x09, 0x9b},
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{0x0b, 0xdf, 0xfc},
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{0x00, 0x00, 0x0d},
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{0x00, 0x58, 0x0f}
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};
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static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = {
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{0x03, 0xf7, 0x90},
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{0x03, 0xf7, 0x90},
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{0x03, 0xe7, 0x90},
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{0x03, 0xe7, 0x90},
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{0x03, 0xf7, 0xa0},
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{0x03, 0xf7, 0xa0},
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{0x03, 0xe7, 0xa0},
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{0x03, 0xe7, 0xa0},
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{0x03, 0xf7, 0xb0},
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{0x03, 0xf7, 0xb0},
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{0x03, 0xe7, 0xb0},
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{0x03, 0xe7, 0xb0},
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{0x03, 0xf7, 0xc0},
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{0x03, 0xe7, 0xc0}
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};
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static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = {
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x06, 0x66, 0x61}
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};
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static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = {
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{0x20, 0x37, 0x90},
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{0x13, 0x33, 0x31},
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{0x84, 0x1f, 0xf2},
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{0x3f, 0xdf, 0xa3},
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{0x7f, 0xd7, 0x84},
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{0x80, 0x2b, 0x55},
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{0x56, 0xaf, 0x36},
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{0xce, 0x02, 0x07},
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{0x6e, 0xbc, 0x98},
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{0x22, 0x1b, 0xb9},
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{0xe0, 0x00, 0x0a},
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{0x08, 0x03, 0x1b},
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{0x00, 0x0a, 0x3c},
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{0xff, 0xff, 0xfd},
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{0x00, 0x00, 0x0e},
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{0x1a, 0xba, 0x8f}
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};
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static u8 al7230_init_table_amode[CB_AL7230_INIT_SEQ][3] = {
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{0x2f, 0xf5, 0x20},
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{0x00, 0x00, 0x01},
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{0x45, 0x1f, 0xe2},
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{0x5f, 0xdf, 0xa3},
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{0x6f, 0xd7, 0x84},
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{0x85, 0x3f, 0x55},
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{0x56, 0xaf, 0x36},
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{0xce, 0x02, 0x07},
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{0x6e, 0xbc, 0x98},
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{0x22, 0x1b, 0xb9},
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{0xe0, 0x60, 0x0a},
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{0x08, 0x03, 0x1b},
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{0x00, 0x14, 0x7c},
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{0xff, 0xff, 0xfd},
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{0x00, 0x00, 0x0e},
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{0x12, 0xba, 0xcf}
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};
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static u8 al7230_channel_table0[CB_MAX_CHANNEL][3] = {
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xc0},
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{0x20, 0x37, 0xc0},
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{0x0f, 0xf5, 0x20}, /* channel 15 Tf = 4915MHz */
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{0x2f, 0xf5, 0x20},
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{0x0f, 0xf5, 0x20},
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{0x0f, 0xf5, 0x20},
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{0x2f, 0xf5, 0x20},
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{0x0f, 0xf5, 0x20},
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{0x2f, 0xf5, 0x30},
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{0x2f, 0xf5, 0x30},
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{0x0f, 0xf5, 0x40},
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{0x2f, 0xf5, 0x40},
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{0x0f, 0xf5, 0x40},
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{0x0f, 0xf5, 0x40},
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{0x2f, 0xf5, 0x40},
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{0x2f, 0xf5, 0x50},
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{0x2f, 0xf5, 0x60},
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{0x2f, 0xf5, 0x60},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x80},
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{0x2f, 0xf5, 0x80},
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{0x2f, 0xf5, 0x80},
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{0x2f, 0xf5, 0x90},
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{0x2f, 0xf5, 0xc0},
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{0x2f, 0xf5, 0xc0},
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{0x2f, 0xf5, 0xc0},
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{0x2f, 0xf5, 0xd0},
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{0x2f, 0xf5, 0xd0},
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{0x2f, 0xf5, 0xd0},
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{0x2f, 0xf5, 0xe0},
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{0x2f, 0xf5, 0xe0},
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{0x2f, 0xf5, 0xe0},
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{0x2f, 0xf5, 0xf0},
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{0x2f, 0xf5, 0xf0},
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{0x2f, 0xf6, 0x00},
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{0x2f, 0xf6, 0x00},
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{0x2f, 0xf6, 0x00},
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{0x2f, 0xf6, 0x10},
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{0x2f, 0xf6, 0x10}
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};
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static u8 al7230_channel_table1[CB_MAX_CHANNEL][3] = {
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{0x13, 0x33, 0x31},
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{0x1b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x13, 0x33, 0x31},
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{0x1b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x13, 0x33, 0x31},
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{0x1b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x13, 0x33, 0x31},
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{0x06, 0x66, 0x61},
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{0x1d, 0x55, 0x51}, /* channel = 15, Tf = 4915MHz */
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{0x00, 0x00, 0x01},
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{0x02, 0xaa, 0xa1},
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{0x08, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x0d, 0x55, 0x51},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x1d, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x02, 0xaa, 0xa1},
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{0x08, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x05, 0x55, 0x51},
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{0x0a, 0xaa, 0xa1},
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{0x10, 0x00, 0x01},
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{0x15, 0x55, 0x51},
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{0x1a, 0xaa, 0xa1},
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{0x00, 0x00, 0x01},
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{0x05, 0x55, 0x51},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x18, 0x00, 0x01},
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{0x02, 0xaa, 0xa1},
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{0x0d, 0x55, 0x51},
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{0x18, 0x00, 0x01},
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{0x02, 0xaa, 0xb1}
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};
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static u8 al7230_channel_table2[CB_MAX_CHANNEL][3] = {
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84}, /* channel = 15 Tf = 4915MHz */
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84}
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};
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static u8 vt3226_init_table[CB_VT3226_INIT_SEQ][3] = {
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{0x03, 0xff, 0x80},
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{0x02, 0x82, 0xa1},
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{0x03, 0xc6, 0xa2},
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{0x01, 0x97, 0x93},
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{0x03, 0x66, 0x64},
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{0x00, 0x61, 0xa5},
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{0x01, 0x7b, 0xd6},
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{0x00, 0x80, 0x17},
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{0x03, 0xf8, 0x08},
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{0x00, 0x02, 0x39},
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{0x02, 0x00, 0x2a}
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};
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static u8 vt3226d0_init_table[CB_VT3226_INIT_SEQ][3] = {
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{0x03, 0xff, 0x80},
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{0x03, 0x02, 0x21},
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{0x03, 0xc6, 0xa2},
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{0x01, 0x97, 0x93},
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{0x03, 0x66, 0x64},
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{0x00, 0x71, 0xa5},
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{0x01, 0x15, 0xc6},
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{0x01, 0x2e, 0x07},
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{0x00, 0x58, 0x08},
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{0x00, 0x02, 0x79},
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{0x02, 0x01, 0xaa}
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};
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static u8 vt3226_channel_table0[CB_MAX_CHANNEL_24G][3] = {
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{0x01, 0x97, 0x83},
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{0x01, 0x97, 0x83},
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{0x01, 0x97, 0x93},
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{0x01, 0x97, 0x93},
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{0x01, 0x97, 0x93},
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{0x01, 0x97, 0x93},
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{0x01, 0x97, 0xa3},
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{0x01, 0x97, 0xa3},
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{0x01, 0x97, 0xa3},
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{0x01, 0x97, 0xa3},
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{0x01, 0x97, 0xb3},
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{0x01, 0x97, 0xb3},
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{0x01, 0x97, 0xb3},
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{0x03, 0x37, 0xc3}
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};
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static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = {
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{0x02, 0x66, 0x64},
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{0x03, 0x66, 0x64},
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{0x00, 0x66, 0x64},
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{0x01, 0x66, 0x64},
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{0x02, 0x66, 0x64},
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{0x03, 0x66, 0x64},
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{0x00, 0x66, 0x64},
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{0x01, 0x66, 0x64},
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{0x02, 0x66, 0x64},
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{0x03, 0x66, 0x64},
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{0x00, 0x66, 0x64},
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{0x01, 0x66, 0x64},
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{0x02, 0x66, 0x64},
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{0x00, 0xcc, 0xc4}
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};
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static const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = {
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0x0135c600,
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0x0135c600,
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0x0235c600,
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0x0235c600,
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0x0235c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0335c600,
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0x0135c600
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};
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static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
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{0x03, 0xff, 0x80},
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{0x02, 0x08, 0x81},
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{0x00, 0xc6, 0x02},
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{0x03, 0xc5, 0x13},
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{0x00, 0xee, 0xe4},
|
|
{0x00, 0x71, 0xa5},
|
|
{0x01, 0x75, 0x46},
|
|
{0x01, 0x40, 0x27},
|
|
{0x01, 0x54, 0x08},
|
|
{0x00, 0x01, 0x69},
|
|
{0x02, 0x00, 0xaa},
|
|
{0x00, 0x08, 0xcb},
|
|
{0x01, 0x70, 0x0c}
|
|
};
|
|
|
|
static u8 vt3342_channel_table0[CB_MAX_CHANNEL][3] = {
|
|
{0x02, 0x05, 0x03},
|
|
{0x01, 0x15, 0x03},
|
|
{0x03, 0xc5, 0x03},
|
|
{0x02, 0x65, 0x03},
|
|
{0x01, 0x15, 0x13},
|
|
{0x03, 0xc5, 0x13},
|
|
{0x02, 0x05, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x03, 0xc5, 0x13},
|
|
{0x02, 0x65, 0x13},
|
|
{0x01, 0x15, 0x23},
|
|
{0x03, 0xc5, 0x23},
|
|
{0x02, 0x05, 0x23},
|
|
{0x00, 0xd5, 0x23},
|
|
{0x01, 0x15, 0x13}, /* channel = 15 Tf = 4915MHz */
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x15, 0x13},
|
|
{0x01, 0x55, 0x63},
|
|
{0x01, 0x55, 0x63},
|
|
{0x02, 0xa5, 0x63},
|
|
{0x02, 0xa5, 0x63},
|
|
{0x00, 0x05, 0x73},
|
|
{0x00, 0x05, 0x73},
|
|
{0x01, 0x55, 0x73},
|
|
{0x02, 0xa5, 0x73},
|
|
{0x00, 0x05, 0x83},
|
|
{0x01, 0x55, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x02, 0xa5, 0x83},
|
|
{0x00, 0x05, 0xF3},
|
|
{0x01, 0x56, 0x03},
|
|
{0x02, 0xa6, 0x03},
|
|
{0x00, 0x06, 0x03},
|
|
{0x00, 0x06, 0x03}
|
|
};
|
|
|
|
static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = {
|
|
{0x01, 0x99, 0x94},
|
|
{0x02, 0x44, 0x44},
|
|
{0x02, 0xee, 0xe4},
|
|
{0x03, 0x99, 0x94},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0xee, 0xe4},
|
|
{0x01, 0x99, 0x94},
|
|
{0x02, 0x44, 0x44},
|
|
{0x02, 0xee, 0xe4},
|
|
{0x03, 0x99, 0x94},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0xee, 0xe4},
|
|
{0x01, 0x99, 0x94},
|
|
{0x03, 0x33, 0x34},
|
|
{0x00, 0x44, 0x44}, /* channel = 15 Tf = 4915MHz */
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x00, 0x44, 0x44},
|
|
{0x01, 0x55, 0x54},
|
|
{0x01, 0x55, 0x54},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x00, 0x00, 0x04},
|
|
{0x00, 0x00, 0x04},
|
|
{0x01, 0x55, 0x54},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x00, 0x00, 0x04},
|
|
{0x01, 0x55, 0x54},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x02, 0xaa, 0xa4},
|
|
{0x03, 0x00, 0x04},
|
|
{0x00, 0x55, 0x54},
|
|
{0x01, 0xaa, 0xa4},
|
|
{0x03, 0x00, 0x04},
|
|
{0x03, 0x00, 0x04}
|
|
};
|
|
|
|
enum {
|
|
VNT_TABLE_INIT = 0,
|
|
VNT_TABLE_INIT_2 = 0,
|
|
VNT_TABLE_0 = 1,
|
|
VNT_TABLE_1 = 2,
|
|
VNT_TABLE_2 = 1
|
|
};
|
|
|
|
struct vnt_table_info {
|
|
u8 *addr;
|
|
int length;
|
|
};
|
|
|
|
static const struct vnt_table_info vnt_table_seq[][3] = {
|
|
{ /* RF_AL2230, RF_AL2230S init table, channel table 0 and 1 */
|
|
{&al2230_init_table[0][0], CB_AL2230_INIT_SEQ * 3},
|
|
{&al2230_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3},
|
|
{&al2230_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3}
|
|
}, { /* RF_AIROHA7230 init table, channel table 0 and 1 */
|
|
{&al7230_init_table[0][0], CB_AL7230_INIT_SEQ * 3},
|
|
{&al7230_channel_table0[0][0], CB_MAX_CHANNEL * 3},
|
|
{&al7230_channel_table1[0][0], CB_MAX_CHANNEL * 3}
|
|
}, { /* RF_VT3226 init table, channel table 0 and 1 */
|
|
{&vt3226_init_table[0][0], CB_VT3226_INIT_SEQ * 3},
|
|
{&vt3226_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3},
|
|
{&vt3226_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3}
|
|
}, { /* RF_VT3226D0 init table, channel table 0 and 1 */
|
|
{&vt3226d0_init_table[0][0], CB_VT3226_INIT_SEQ * 3},
|
|
{&vt3226_channel_table0[0][0], CB_MAX_CHANNEL_24G * 3},
|
|
{&vt3226_channel_table1[0][0], CB_MAX_CHANNEL_24G * 3}
|
|
}, { /* RF_VT3342A0 init table, channel table 0 and 1 */
|
|
{&vt3342a0_init_table[0][0], CB_VT3342_INIT_SEQ * 3},
|
|
{&vt3342_channel_table0[0][0], CB_MAX_CHANNEL * 3},
|
|
{&vt3342_channel_table1[0][0], CB_MAX_CHANNEL * 3}
|
|
}, { /* RF_AIROHA7230 init table 2 and channel table 2 */
|
|
{&al7230_init_table_amode[0][0], CB_AL7230_INIT_SEQ * 3},
|
|
{&al7230_channel_table2[0][0], CB_MAX_CHANNEL * 3},
|
|
{NULL, 0}
|
|
}
|
|
};
|
|
|
|
/*
|
|
* Description: Write to IF/RF, by embedded programming
|
|
*/
|
|
int vnt_rf_write_embedded(struct vnt_private *priv, u32 data)
|
|
{
|
|
u8 reg_data[4];
|
|
|
|
data |= (VNT_RF_REG_LEN << 3) | IFREGCTL_REGW;
|
|
|
|
reg_data[0] = (u8)data;
|
|
reg_data[1] = (u8)(data >> 8);
|
|
reg_data[2] = (u8)(data >> 16);
|
|
reg_data[3] = (u8)(data >> 24);
|
|
|
|
return vnt_control_out(priv, MESSAGE_TYPE_WRITE_IFRF, 0, 0,
|
|
ARRAY_SIZE(reg_data), reg_data);
|
|
}
|
|
|
|
static u8 vnt_rf_addpower(struct vnt_private *priv)
|
|
{
|
|
int base;
|
|
s32 rssi = -priv->current_rssi;
|
|
|
|
if (!rssi)
|
|
return 7;
|
|
|
|
if (priv->rf_type == RF_VT3226D0)
|
|
base = -60;
|
|
else
|
|
base = -70;
|
|
|
|
if (rssi < base)
|
|
return ((rssi - base + 1) / -5) * 2 + 5;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Set Tx power by power level and rate */
|
|
static int vnt_rf_set_txpower(struct vnt_private *priv, u8 power,
|
|
struct ieee80211_channel *ch)
|
|
{
|
|
u32 power_setting = 0;
|
|
int ret = 0;
|
|
|
|
power += vnt_rf_addpower(priv);
|
|
if (power > VNT_RF_MAX_POWER)
|
|
power = VNT_RF_MAX_POWER;
|
|
|
|
if (priv->power == power)
|
|
return 0;
|
|
|
|
priv->power = power;
|
|
|
|
switch (priv->rf_type) {
|
|
case RF_AL2230:
|
|
power_setting = 0x0404090 | (power << 12);
|
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM)
|
|
ret = vnt_rf_write_embedded(priv, 0x0001b400);
|
|
else
|
|
ret = vnt_rf_write_embedded(priv, 0x0005a400);
|
|
|
|
break;
|
|
case RF_AL2230S:
|
|
power_setting = 0x0404090 | (power << 12);
|
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
|
|
ret = vnt_rf_write_embedded(priv, 0x040c1400);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00299b00);
|
|
} else {
|
|
ret = vnt_rf_write_embedded(priv, 0x0005a400);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00099b00);
|
|
}
|
|
|
|
break;
|
|
|
|
case RF_AIROHA7230:
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM)
|
|
ret = vnt_rf_write_embedded(priv, 0x111bb900);
|
|
else
|
|
ret = vnt_rf_write_embedded(priv, 0x221bb900);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* 0x080F1B00 for 3 wire control TxGain(D10)
|
|
* and 0x31 as TX Gain value
|
|
*/
|
|
power_setting = 0x080c0b00 | (power << 12);
|
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
break;
|
|
|
|
case RF_VT3226:
|
|
power_setting = ((0x3f - power) << 20) | (0x17 << 8);
|
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
break;
|
|
case RF_VT3226D0:
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
|
|
u16 hw_value = ch->hw_value;
|
|
|
|
power_setting = ((0x3f - power) << 20) | (0xe07 << 8);
|
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x03c6a200);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_dbg(&priv->usb->dev,
|
|
"%s 11b channel [%d]\n", __func__, hw_value);
|
|
|
|
hw_value--;
|
|
|
|
if (hw_value < ARRAY_SIZE(vt3226d0_lo_current_table)) {
|
|
ret = vnt_rf_write_embedded(priv,
|
|
vt3226d0_lo_current_table[hw_value]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x015C0800);
|
|
} else {
|
|
dev_dbg(&priv->usb->dev,
|
|
"@@@@ %s> 11G mode\n", __func__);
|
|
|
|
power_setting = ((0x3f - power) << 20) | (0x7 << 8);
|
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00C6A200);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x016BC600);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00900800);
|
|
}
|
|
|
|
break;
|
|
|
|
case RF_VT3342A0:
|
|
power_setting = ((0x3f - power) << 20) | (0x27 << 8);
|
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/* Set Tx power by channel number type */
|
|
int vnt_rf_setpower(struct vnt_private *priv,
|
|
struct ieee80211_channel *ch)
|
|
{
|
|
u16 channel;
|
|
u8 power = priv->cck_pwr;
|
|
|
|
if (!ch)
|
|
return -EINVAL;
|
|
|
|
/* set channel number to array number */
|
|
channel = ch->hw_value - 1;
|
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
|
|
if (channel < ARRAY_SIZE(priv->cck_pwr_tbl))
|
|
power = priv->cck_pwr_tbl[channel];
|
|
} else if (ch->band == NL80211_BAND_5GHZ) {
|
|
/* remove 14 channels to array size */
|
|
channel -= 14;
|
|
|
|
if (channel < ARRAY_SIZE(priv->ofdm_a_pwr_tbl))
|
|
power = priv->ofdm_a_pwr_tbl[channel];
|
|
} else {
|
|
if (channel < ARRAY_SIZE(priv->ofdm_pwr_tbl))
|
|
power = priv->ofdm_pwr_tbl[channel];
|
|
}
|
|
|
|
return vnt_rf_set_txpower(priv, power, ch);
|
|
}
|
|
|
|
/* Convert rssi to dbm */
|
|
void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm)
|
|
{
|
|
u8 idx = ((rssi & 0xc0) >> 6) & 0x03;
|
|
long b = rssi & 0x3f;
|
|
long a = 0;
|
|
u8 airoharf[4] = {0, 18, 0, 40};
|
|
|
|
switch (priv->rf_type) {
|
|
case RF_AL2230:
|
|
case RF_AL2230S:
|
|
case RF_AIROHA7230:
|
|
case RF_VT3226:
|
|
case RF_VT3226D0:
|
|
case RF_VT3342A0:
|
|
a = airoharf[idx];
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
*dbm = -1 * (a + b * 2);
|
|
}
|
|
|
|
int vnt_rf_table_download(struct vnt_private *priv)
|
|
{
|
|
int ret;
|
|
int idx = -1;
|
|
const struct vnt_table_info *table_seq;
|
|
|
|
switch (priv->rf_type) {
|
|
case RF_AL2230:
|
|
case RF_AL2230S:
|
|
idx = 0;
|
|
break;
|
|
case RF_AIROHA7230:
|
|
idx = 1;
|
|
break;
|
|
case RF_VT3226:
|
|
idx = 2;
|
|
break;
|
|
case RF_VT3226D0:
|
|
idx = 3;
|
|
break;
|
|
case RF_VT3342A0:
|
|
idx = 4;
|
|
break;
|
|
}
|
|
|
|
if (idx < 0)
|
|
return 0;
|
|
|
|
table_seq = &vnt_table_seq[idx][0];
|
|
|
|
/* Init Table */
|
|
ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
|
|
MESSAGE_REQUEST_RF_INIT,
|
|
table_seq[VNT_TABLE_INIT].length,
|
|
table_seq[VNT_TABLE_INIT].addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Channel Table 0 */
|
|
ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
|
|
MESSAGE_REQUEST_RF_CH0,
|
|
table_seq[VNT_TABLE_0].length,
|
|
table_seq[VNT_TABLE_0].addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Channel Table 1 */
|
|
ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
|
|
MESSAGE_REQUEST_RF_CH1,
|
|
table_seq[VNT_TABLE_1].length,
|
|
table_seq[VNT_TABLE_1].addr);
|
|
|
|
if (priv->rf_type == RF_AIROHA7230) {
|
|
table_seq = &vnt_table_seq[5][0];
|
|
|
|
/* Init Table 2 */
|
|
ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
|
|
MESSAGE_REQUEST_RF_INIT2,
|
|
table_seq[VNT_TABLE_INIT_2].length,
|
|
table_seq[VNT_TABLE_INIT_2].addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Channel Table 2 */
|
|
ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
|
|
MESSAGE_REQUEST_RF_CH2,
|
|
table_seq[VNT_TABLE_2].length,
|
|
table_seq[VNT_TABLE_2].addr);
|
|
}
|
|
|
|
return ret;
|
|
}
|