Ben Widawsky 80d10a6cee cxl/region: Add interleave geometry attributes ... Add ABI to allow the number of devices that comprise a region to be set as well as the interleave granularity for the region. Signed-off-by: Ben Widawsky <bwidawsk@kernel.org> [djbw: reword changelog] Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220624041950.559155-11-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-07-25 12:18:06 -07:00
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core	cxl/region: Add interleave geometry attributes	2022-07-25 12:18:06 -07:00
acpi.c	cxl/port: Record parent dport when adding ports	2022-07-21 17:19:24 -07:00
cxl.h	cxl/region: Add interleave geometry attributes	2022-07-25 12:18:06 -07:00
cxlmem.h	cxl/hdm: Enumerate allocated DPA	2022-07-21 17:19:12 -07:00
cxlpci.h	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00
Kconfig	cxl/region: Add region creation support	2022-07-21 17:19:25 -07:00
Makefile	PM: CXL: Disable suspend	2022-04-22 16:09:42 -07:00
mem.c	cxl/mem: Enumerate port targets before adding endpoints	2022-07-21 17:19:25 -07:00
pci.c	cxl/pci: Create PCI DOE mailbox's for memory devices	2022-07-19 15:38:04 -07:00
pmem.c	cxl/mbox: Use __le32 in get,set_lsa mailbox structures	2022-06-21 14:09:00 -07:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00