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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Peter Zijlstra](/assets/img/avatar_default.png)
commit6690e86be8
upstream. Effectively reverts commit:2c7577a758
("sched/x86_64: Don't save flags on context switch") Specifically because SMAP uses FLAGS.AC which invalidates the claim that the kernel has clean flags. In particular; while preemption from interrupt return is fine (the IRET frame on the exception stack contains FLAGS) it breaks any code that does synchonous scheduling, including preempt_enable(). This has become a significant issue ever since commit:5b24a7a2aa
("Add 'unsafe' user access functions for batched accesses") provided for means of having 'normal' C code between STAC / CLAC, exposing the FLAGS.AC state. So far this hasn't led to trouble, however fix it before it comes apart. Reported-by: Julien Thierry <julien.thierry@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: stable@kernel.org Fixes:5b24a7a2aa
("Add 'unsafe' user access functions for batched accesses") Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
706 lines
19 KiB
C
706 lines
19 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*
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* X86-64 port
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* Andi Kleen.
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*
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* CPU hotplug support - ashok.raj@intel.com
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*/
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/*
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* This file handles the architecture-dependent parts of process handling..
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*/
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#include <linux/cpu.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/fs.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/elfcore.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/ptrace.h>
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#include <linux/notifier.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <linux/prctl.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <linux/ftrace.h>
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#include <linux/syscalls.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/fpu/internal.h>
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#include <asm/mmu_context.h>
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#include <asm/prctl.h>
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#include <asm/desc.h>
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#include <asm/proto.h>
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#include <asm/ia32.h>
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#include <asm/syscalls.h>
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#include <asm/debugreg.h>
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#include <asm/switch_to.h>
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#include <asm/xen/hypervisor.h>
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#include <asm/vdso.h>
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#include <asm/intel_rdt_sched.h>
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#include <asm/unistd.h>
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#ifdef CONFIG_IA32_EMULATION
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/* Not included via unistd.h */
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#include <asm/unistd_32_ia32.h>
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#endif
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#include "process.h"
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__visible DEFINE_PER_CPU(unsigned long, rsp_scratch);
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/* Prints also some state that isn't saved in the pt_regs */
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void __show_regs(struct pt_regs *regs, int all)
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{
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unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
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unsigned long d0, d1, d2, d3, d6, d7;
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unsigned int fsindex, gsindex;
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unsigned int ds, cs, es;
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show_iret_regs(regs);
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if (regs->orig_ax != -1)
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pr_cont(" ORIG_RAX: %016lx\n", regs->orig_ax);
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else
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pr_cont("\n");
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printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
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regs->ax, regs->bx, regs->cx);
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printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
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regs->dx, regs->si, regs->di);
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printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
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regs->bp, regs->r8, regs->r9);
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printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
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regs->r10, regs->r11, regs->r12);
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printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
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regs->r13, regs->r14, regs->r15);
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if (!all)
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return;
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asm("movl %%ds,%0" : "=r" (ds));
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asm("movl %%cs,%0" : "=r" (cs));
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asm("movl %%es,%0" : "=r" (es));
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asm("movl %%fs,%0" : "=r" (fsindex));
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asm("movl %%gs,%0" : "=r" (gsindex));
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rdmsrl(MSR_FS_BASE, fs);
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rdmsrl(MSR_GS_BASE, gs);
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rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
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cr0 = read_cr0();
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cr2 = read_cr2();
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cr3 = __read_cr3();
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cr4 = __read_cr4();
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printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
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fs, fsindex, gs, gsindex, shadowgs);
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printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
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es, cr0);
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printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
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cr4);
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get_debugreg(d0, 0);
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get_debugreg(d1, 1);
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get_debugreg(d2, 2);
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get_debugreg(d3, 3);
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get_debugreg(d6, 6);
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get_debugreg(d7, 7);
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/* Only print out debug registers if they are in their non-default state. */
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if (!((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
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(d6 == DR6_RESERVED) && (d7 == 0x400))) {
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printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n",
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d0, d1, d2);
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printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n",
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d3, d6, d7);
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}
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if (boot_cpu_has(X86_FEATURE_OSPKE))
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printk(KERN_DEFAULT "PKRU: %08x\n", read_pkru());
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}
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void release_thread(struct task_struct *dead_task)
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{
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if (dead_task->mm) {
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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if (dead_task->mm->context.ldt) {
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pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
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dead_task->comm,
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dead_task->mm->context.ldt->entries,
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dead_task->mm->context.ldt->nr_entries);
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BUG();
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}
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#endif
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}
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}
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enum which_selector {
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FS,
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GS
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};
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/*
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* Saves the FS or GS base for an outgoing thread if FSGSBASE extensions are
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* not available. The goal is to be reasonably fast on non-FSGSBASE systems.
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* It's forcibly inlined because it'll generate better code and this function
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* is hot.
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*/
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static __always_inline void save_base_legacy(struct task_struct *prev_p,
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unsigned short selector,
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enum which_selector which)
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{
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if (likely(selector == 0)) {
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/*
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* On Intel (without X86_BUG_NULL_SEG), the segment base could
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* be the pre-existing saved base or it could be zero. On AMD
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* (with X86_BUG_NULL_SEG), the segment base could be almost
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* anything.
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*
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* This branch is very hot (it's hit twice on almost every
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* context switch between 64-bit programs), and avoiding
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* the RDMSR helps a lot, so we just assume that whatever
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* value is already saved is correct. This matches historical
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* Linux behavior, so it won't break existing applications.
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*
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* To avoid leaking state, on non-X86_BUG_NULL_SEG CPUs, if we
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* report that the base is zero, it needs to actually be zero:
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* see the corresponding logic in load_seg_legacy.
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*/
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} else {
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/*
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* If the selector is 1, 2, or 3, then the base is zero on
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* !X86_BUG_NULL_SEG CPUs and could be anything on
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* X86_BUG_NULL_SEG CPUs. In the latter case, Linux
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* has never attempted to preserve the base across context
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* switches.
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*
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* If selector > 3, then it refers to a real segment, and
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* saving the base isn't necessary.
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*/
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if (which == FS)
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prev_p->thread.fsbase = 0;
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else
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prev_p->thread.gsbase = 0;
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}
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}
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static __always_inline void save_fsgs(struct task_struct *task)
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{
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savesegment(fs, task->thread.fsindex);
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savesegment(gs, task->thread.gsindex);
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save_base_legacy(task, task->thread.fsindex, FS);
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save_base_legacy(task, task->thread.gsindex, GS);
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}
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static __always_inline void loadseg(enum which_selector which,
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unsigned short sel)
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{
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if (which == FS)
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loadsegment(fs, sel);
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else
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load_gs_index(sel);
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}
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static __always_inline void load_seg_legacy(unsigned short prev_index,
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unsigned long prev_base,
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unsigned short next_index,
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unsigned long next_base,
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enum which_selector which)
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{
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if (likely(next_index <= 3)) {
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/*
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* The next task is using 64-bit TLS, is not using this
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* segment at all, or is having fun with arcane CPU features.
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*/
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if (next_base == 0) {
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/*
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* Nasty case: on AMD CPUs, we need to forcibly zero
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* the base.
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*/
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if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
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loadseg(which, __USER_DS);
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loadseg(which, next_index);
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} else {
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/*
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* We could try to exhaustively detect cases
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* under which we can skip the segment load,
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* but there's really only one case that matters
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* for performance: if both the previous and
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* next states are fully zeroed, we can skip
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* the load.
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*
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* (This assumes that prev_base == 0 has no
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* false positives. This is the case on
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* Intel-style CPUs.)
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*/
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if (likely(prev_index | next_index | prev_base))
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loadseg(which, next_index);
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}
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} else {
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if (prev_index != next_index)
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loadseg(which, next_index);
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wrmsrl(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE,
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next_base);
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}
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} else {
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/*
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* The next task is using a real segment. Loading the selector
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* is sufficient.
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*/
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loadseg(which, next_index);
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}
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}
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int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
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unsigned long arg, struct task_struct *p, unsigned long tls)
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{
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int err;
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struct pt_regs *childregs;
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struct fork_frame *fork_frame;
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struct inactive_task_frame *frame;
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struct task_struct *me = current;
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childregs = task_pt_regs(p);
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fork_frame = container_of(childregs, struct fork_frame, regs);
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frame = &fork_frame->frame;
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/*
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* For a new task use the RESET flags value since there is no before.
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* All the status flags are zero; DF and all the system flags must also
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* be 0, specifically IF must be 0 because we context switch to the new
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* task with interrupts disabled.
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*/
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frame->flags = X86_EFLAGS_FIXED;
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frame->bp = 0;
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frame->ret_addr = (unsigned long) ret_from_fork;
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p->thread.sp = (unsigned long) fork_frame;
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p->thread.io_bitmap_ptr = NULL;
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savesegment(gs, p->thread.gsindex);
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p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase;
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savesegment(fs, p->thread.fsindex);
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p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase;
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savesegment(es, p->thread.es);
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savesegment(ds, p->thread.ds);
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memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
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if (unlikely(p->flags & PF_KTHREAD)) {
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/* kernel thread */
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memset(childregs, 0, sizeof(struct pt_regs));
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frame->bx = sp; /* function */
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frame->r12 = arg;
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return 0;
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}
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frame->bx = 0;
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*childregs = *current_pt_regs();
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childregs->ax = 0;
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if (sp)
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childregs->sp = sp;
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err = -ENOMEM;
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if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
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p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr,
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IO_BITMAP_BYTES, GFP_KERNEL);
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if (!p->thread.io_bitmap_ptr) {
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p->thread.io_bitmap_max = 0;
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return -ENOMEM;
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}
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set_tsk_thread_flag(p, TIF_IO_BITMAP);
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}
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/*
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* Set a new TLS for the child thread?
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*/
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if (clone_flags & CLONE_SETTLS) {
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#ifdef CONFIG_IA32_EMULATION
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if (in_ia32_syscall())
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err = do_set_thread_area(p, -1,
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(struct user_desc __user *)tls, 0);
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else
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#endif
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err = do_arch_prctl_64(p, ARCH_SET_FS, tls);
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if (err)
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goto out;
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}
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err = 0;
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out:
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if (err && p->thread.io_bitmap_ptr) {
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kfree(p->thread.io_bitmap_ptr);
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p->thread.io_bitmap_max = 0;
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}
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return err;
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}
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static void
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start_thread_common(struct pt_regs *regs, unsigned long new_ip,
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unsigned long new_sp,
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unsigned int _cs, unsigned int _ss, unsigned int _ds)
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{
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WARN_ON_ONCE(regs != current_pt_regs());
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if (static_cpu_has(X86_BUG_NULL_SEG)) {
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/* Loading zero below won't clear the base. */
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loadsegment(fs, __USER_DS);
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load_gs_index(__USER_DS);
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}
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loadsegment(fs, 0);
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loadsegment(es, _ds);
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loadsegment(ds, _ds);
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load_gs_index(0);
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regs->ip = new_ip;
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regs->sp = new_sp;
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regs->cs = _cs;
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regs->ss = _ss;
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regs->flags = X86_EFLAGS_IF;
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force_iret();
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}
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void
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start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
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{
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start_thread_common(regs, new_ip, new_sp,
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__USER_CS, __USER_DS, 0);
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}
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EXPORT_SYMBOL_GPL(start_thread);
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#ifdef CONFIG_COMPAT
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void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp)
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{
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start_thread_common(regs, new_ip, new_sp,
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test_thread_flag(TIF_X32)
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? __USER_CS : __USER32_CS,
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__USER_DS, __USER_DS);
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}
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#endif
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/*
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* switch_to(x,y) should switch tasks from x to y.
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*
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* This could still be optimized:
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* - fold all the options into a flag word and test it with a single test.
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* - could test fs/gs bitsliced
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*
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* Kprobes not supported here. Set the probe on schedule instead.
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* Function graph tracer not supported too.
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*/
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__visible __notrace_funcgraph struct task_struct *
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__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
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{
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struct thread_struct *prev = &prev_p->thread;
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struct thread_struct *next = &next_p->thread;
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struct fpu *prev_fpu = &prev->fpu;
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struct fpu *next_fpu = &next->fpu;
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int cpu = smp_processor_id();
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WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
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this_cpu_read(irq_count) != -1);
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switch_fpu_prepare(prev_fpu, cpu);
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/* We must save %fs and %gs before load_TLS() because
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* %fs and %gs may be cleared by load_TLS().
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*
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* (e.g. xen_load_tls())
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*/
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save_fsgs(prev_p);
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/*
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* Load TLS before restoring any segments so that segment loads
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* reference the correct GDT entries.
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*/
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load_TLS(next, cpu);
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/*
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* Leave lazy mode, flushing any hypercalls made here. This
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* must be done after loading TLS entries in the GDT but before
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* loading segments that might reference them, and and it must
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* be done before fpu__restore(), so the TS bit is up to
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* date.
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*/
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arch_end_context_switch(next_p);
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/* Switch DS and ES.
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*
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* Reading them only returns the selectors, but writing them (if
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* nonzero) loads the full descriptor from the GDT or LDT. The
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* LDT for next is loaded in switch_mm, and the GDT is loaded
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* above.
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*
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* We therefore need to write new values to the segment
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* registers on every context switch unless both the new and old
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* values are zero.
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*
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* Note that we don't need to do anything for CS and SS, as
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* those are saved and restored as part of pt_regs.
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*/
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savesegment(es, prev->es);
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if (unlikely(next->es | prev->es))
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loadsegment(es, next->es);
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savesegment(ds, prev->ds);
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if (unlikely(next->ds | prev->ds))
|
|
loadsegment(ds, next->ds);
|
|
|
|
load_seg_legacy(prev->fsindex, prev->fsbase,
|
|
next->fsindex, next->fsbase, FS);
|
|
load_seg_legacy(prev->gsindex, prev->gsbase,
|
|
next->gsindex, next->gsbase, GS);
|
|
|
|
switch_fpu_finish(next_fpu, cpu);
|
|
|
|
/*
|
|
* Switch the PDA and FPU contexts.
|
|
*/
|
|
this_cpu_write(current_task, next_p);
|
|
this_cpu_write(cpu_current_top_of_stack, task_top_of_stack(next_p));
|
|
|
|
/* Reload sp0. */
|
|
update_sp0(next_p);
|
|
|
|
__switch_to_xtra(prev_p, next_p);
|
|
|
|
#ifdef CONFIG_XEN_PV
|
|
/*
|
|
* On Xen PV, IOPL bits in pt_regs->flags have no effect, and
|
|
* current_pt_regs()->flags may not match the current task's
|
|
* intended IOPL. We need to switch it manually.
|
|
*/
|
|
if (unlikely(static_cpu_has(X86_FEATURE_XENPV) &&
|
|
prev->iopl != next->iopl))
|
|
xen_set_iopl_mask(next->iopl);
|
|
#endif
|
|
|
|
if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) {
|
|
/*
|
|
* AMD CPUs have a misfeature: SYSRET sets the SS selector but
|
|
* does not update the cached descriptor. As a result, if we
|
|
* do SYSRET while SS is NULL, we'll end up in user mode with
|
|
* SS apparently equal to __USER_DS but actually unusable.
|
|
*
|
|
* The straightforward workaround would be to fix it up just
|
|
* before SYSRET, but that would slow down the system call
|
|
* fast paths. Instead, we ensure that SS is never NULL in
|
|
* system call context. We do this by replacing NULL SS
|
|
* selectors at every context switch. SYSCALL sets up a valid
|
|
* SS, so the only way to get NULL is to re-enter the kernel
|
|
* from CPL 3 through an interrupt. Since that can't happen
|
|
* in the same task as a running syscall, we are guaranteed to
|
|
* context switch between every interrupt vector entry and a
|
|
* subsequent SYSRET.
|
|
*
|
|
* We read SS first because SS reads are much faster than
|
|
* writes. Out of caution, we force SS to __KERNEL_DS even if
|
|
* it previously had a different non-NULL value.
|
|
*/
|
|
unsigned short ss_sel;
|
|
savesegment(ss, ss_sel);
|
|
if (ss_sel != __KERNEL_DS)
|
|
loadsegment(ss, __KERNEL_DS);
|
|
}
|
|
|
|
/* Load the Intel cache allocation PQR MSR. */
|
|
intel_rdt_sched_in();
|
|
|
|
return prev_p;
|
|
}
|
|
|
|
void set_personality_64bit(void)
|
|
{
|
|
/* inherit personality from parent */
|
|
|
|
/* Make sure to be in 64bit mode */
|
|
clear_thread_flag(TIF_IA32);
|
|
clear_thread_flag(TIF_ADDR32);
|
|
clear_thread_flag(TIF_X32);
|
|
/* Pretend that this comes from a 64bit execve */
|
|
task_pt_regs(current)->orig_ax = __NR_execve;
|
|
current_thread_info()->status &= ~TS_COMPAT;
|
|
|
|
/* Ensure the corresponding mm is not marked. */
|
|
if (current->mm)
|
|
current->mm->context.ia32_compat = 0;
|
|
|
|
/* TBD: overwrites user setup. Should have two bits.
|
|
But 64bit processes have always behaved this way,
|
|
so it's not too bad. The main problem is just that
|
|
32bit childs are affected again. */
|
|
current->personality &= ~READ_IMPLIES_EXEC;
|
|
}
|
|
|
|
static void __set_personality_x32(void)
|
|
{
|
|
#ifdef CONFIG_X86_X32
|
|
clear_thread_flag(TIF_IA32);
|
|
set_thread_flag(TIF_X32);
|
|
if (current->mm)
|
|
current->mm->context.ia32_compat = TIF_X32;
|
|
current->personality &= ~READ_IMPLIES_EXEC;
|
|
/*
|
|
* in_compat_syscall() uses the presence of the x32 syscall bit
|
|
* flag to determine compat status. The x86 mmap() code relies on
|
|
* the syscall bitness so set x32 syscall bit right here to make
|
|
* in_compat_syscall() work during exec().
|
|
*
|
|
* Pretend to come from a x32 execve.
|
|
*/
|
|
task_pt_regs(current)->orig_ax = __NR_x32_execve | __X32_SYSCALL_BIT;
|
|
current_thread_info()->status &= ~TS_COMPAT;
|
|
#endif
|
|
}
|
|
|
|
static void __set_personality_ia32(void)
|
|
{
|
|
#ifdef CONFIG_IA32_EMULATION
|
|
set_thread_flag(TIF_IA32);
|
|
clear_thread_flag(TIF_X32);
|
|
if (current->mm)
|
|
current->mm->context.ia32_compat = TIF_IA32;
|
|
current->personality |= force_personality32;
|
|
/* Prepare the first "return" to user space */
|
|
task_pt_regs(current)->orig_ax = __NR_ia32_execve;
|
|
current_thread_info()->status |= TS_COMPAT;
|
|
#endif
|
|
}
|
|
|
|
void set_personality_ia32(bool x32)
|
|
{
|
|
/* Make sure to be in 32bit mode */
|
|
set_thread_flag(TIF_ADDR32);
|
|
|
|
if (x32)
|
|
__set_personality_x32();
|
|
else
|
|
__set_personality_ia32();
|
|
}
|
|
EXPORT_SYMBOL_GPL(set_personality_ia32);
|
|
|
|
#ifdef CONFIG_CHECKPOINT_RESTORE
|
|
static long prctl_map_vdso(const struct vdso_image *image, unsigned long addr)
|
|
{
|
|
int ret;
|
|
|
|
ret = map_vdso_once(image, addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return (long)image->size;
|
|
}
|
|
#endif
|
|
|
|
long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2)
|
|
{
|
|
int ret = 0;
|
|
int doit = task == current;
|
|
int cpu;
|
|
|
|
switch (option) {
|
|
case ARCH_SET_GS:
|
|
if (arg2 >= TASK_SIZE_MAX)
|
|
return -EPERM;
|
|
cpu = get_cpu();
|
|
task->thread.gsindex = 0;
|
|
task->thread.gsbase = arg2;
|
|
if (doit) {
|
|
load_gs_index(0);
|
|
ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, arg2);
|
|
}
|
|
put_cpu();
|
|
break;
|
|
case ARCH_SET_FS:
|
|
/* Not strictly needed for fs, but do it for symmetry
|
|
with gs */
|
|
if (arg2 >= TASK_SIZE_MAX)
|
|
return -EPERM;
|
|
cpu = get_cpu();
|
|
task->thread.fsindex = 0;
|
|
task->thread.fsbase = arg2;
|
|
if (doit) {
|
|
/* set the selector to 0 to not confuse __switch_to */
|
|
loadsegment(fs, 0);
|
|
ret = wrmsrl_safe(MSR_FS_BASE, arg2);
|
|
}
|
|
put_cpu();
|
|
break;
|
|
case ARCH_GET_FS: {
|
|
unsigned long base;
|
|
|
|
if (doit)
|
|
rdmsrl(MSR_FS_BASE, base);
|
|
else
|
|
base = task->thread.fsbase;
|
|
ret = put_user(base, (unsigned long __user *)arg2);
|
|
break;
|
|
}
|
|
case ARCH_GET_GS: {
|
|
unsigned long base;
|
|
|
|
if (doit)
|
|
rdmsrl(MSR_KERNEL_GS_BASE, base);
|
|
else
|
|
base = task->thread.gsbase;
|
|
ret = put_user(base, (unsigned long __user *)arg2);
|
|
break;
|
|
}
|
|
|
|
#ifdef CONFIG_CHECKPOINT_RESTORE
|
|
# ifdef CONFIG_X86_X32_ABI
|
|
case ARCH_MAP_VDSO_X32:
|
|
return prctl_map_vdso(&vdso_image_x32, arg2);
|
|
# endif
|
|
# if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
|
|
case ARCH_MAP_VDSO_32:
|
|
return prctl_map_vdso(&vdso_image_32, arg2);
|
|
# endif
|
|
case ARCH_MAP_VDSO_64:
|
|
return prctl_map_vdso(&vdso_image_64, arg2);
|
|
#endif
|
|
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
|
|
{
|
|
long ret;
|
|
|
|
ret = do_arch_prctl_64(current, option, arg2);
|
|
if (ret == -EINVAL)
|
|
ret = do_arch_prctl_common(current, option, arg2);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_IA32_EMULATION
|
|
COMPAT_SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
|
|
{
|
|
return do_arch_prctl_common(current, option, arg2);
|
|
}
|
|
#endif
|
|
|
|
unsigned long KSTK_ESP(struct task_struct *task)
|
|
{
|
|
return task_pt_regs(task)->sp;
|
|
}
|