Robin Murphy d0365cb720 iommu/arm-smmu: Avoid constant zero in TLBI writes ... commit 4e4abae311 upstream. Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU global register space are still, in fact, using a hypervisor to mediate it by trapping and emulating register accesses. Sadly, some deployed versions of said trapping code have bugs wherein they go horribly wrong for stores using r31 (i.e. XZR/WZR) as the source register. While this can be mitigated for GCC today by tweaking the constraints for the implementation of writel_relaxed(), to avoid any potential arms race with future compilers more aggressively optimising register allocation, the simple way is to just remove all the problematic constant zeros. For the write-only TLB operations, the actual value is irrelevant anyway and any old nearby variable will provide a suitable GPR to encode. The one point at which we really do need a zero to clear a context bank happens before any of the TLB maintenance where crashes have been reported, so is apparently not a problem... :/ Reported-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Acked-by: Will Deacon <will.deacon@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2019-06-19 08:20:55 +02:00
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amd_iommu.c	iommu/amd: Reserve exclusion range in iova-domain	2019-05-04 09:15:22 +02:00
amd_iommu_init.c	iommu/amd: Set exclusion range correctly	2019-05-10 17:53:13 +02:00
amd_iommu_proto.h
amd_iommu_types.h	iommu/amd: Reserve exclusion range in iova-domain	2019-05-04 09:15:22 +02:00
amd_iommu_v2.c
arm-smmu-regs.h
arm-smmu-v3.c	iommu/arm-smmu-v3: Use explicit mb() when moving cons pointer	2019-02-12 19:46:03 +01:00
arm-smmu.c	iommu/arm-smmu: Avoid constant zero in TLBI writes	2019-06-19 08:20:55 +02:00
dma-iommu.c
dmar.c	iommu/dmar: Fix buffer overflow during PCI bus notification	2019-04-20 09:15:06 +02:00
exynos-iommu.c	iommu/exynos: Don't unconditionally steal bus ops	2018-04-26 11:02:06 +02:00
fsl_pamu.c
fsl_pamu.h
fsl_pamu_domain.c
fsl_pamu_domain.h
intel-iommu.c	iommu/vt-d: Set intel_iommu_gfx_mapped correctly	2019-06-15 11:54:54 +02:00
intel-svm.c	iommu/vt-d: Fix NULL pointer dereference in prq_event_thread()	2018-12-13 09:18:46 +01:00
intel_irq_remapping.c
io-pgtable-arm-v7s.c	iommu/io-pgtable-arm-v7s: Only kmemleak_ignore L2 tables	2019-04-05 22:31:30 +02:00
io-pgtable-arm.c
io-pgtable.c
io-pgtable.h
iommu-sysfs.c
iommu-traces.c
iommu.c
iova.c
ipmmu-vmsa.c	iommu/ipmmu-vmsa: Fix crash on early domain free	2018-12-13 09:18:46 +01:00
irq_remapping.c
irq_remapping.h
Kconfig
Makefile
msm_iommu.c	iommu/msm: Don't call iommu_device_{,un}link from atomic context	2018-10-03 17:00:47 -07:00
msm_iommu.h
msm_iommu_hw-8xxx.h
mtk_iommu.c	iommu/mediatek: Fix protect memory setting	2018-05-30 07:52:30 +02:00
mtk_iommu.h	iommu/mediatek: Fix protect memory setting	2018-05-30 07:52:30 +02:00
mtk_iommu_v1.c
of_iommu.c
omap-iommu-debug.c
omap-iommu.c	iommu/omap: Fix cache flushes on L2 table entries	2018-09-15 09:45:31 +02:00
omap-iommu.h
omap-iopgtable.h
qcom_iommu.c
rockchip-iommu.c
s390-iommu.c
tegra-gart.c
tegra-smmu.c	iommu/tegra-smmu: Fix invalid ASID bits on Tegra30/114	2019-05-25 18:25:22 +02:00