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9ab57658a6
This patch fixes a few bugs: 1- We weren't taking into account sha_leftovers when adding multiple ksvs to sha_text. As such, we were or'ing the end of ksv[j - 1] with the beginning of ksv[j] 2- In the sha_leftovers == 2 and sha_leftovers == 3 case, bstatus was being placed on the wrong half of sha_text, overlapping the leftover ksv value 3- In the sha_leftovers == 2 case, we need to manually terminate the byte stream with 0x80 since the hardware doesn't have enough room to add it after writing M0 The upside is that all of the HDCP supported HDMI repeaters I could find on Amazon just strip HDCP anyways, so it turns out to be _really_ hard to hit any of these cases without an MST hub, which is not (yet) supported. Oh, and the sha_leftovers == 1 case works perfectly! Fixes:ee5e5e7a5e("drm/i915: Add HDCP framework + base implementation") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v4.17+ Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200818153910.27894-2-sean@poorly.run (cherry picked from commit1f0882214f) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
305 lines
8.7 KiB
C
305 lines
8.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2017 Google, Inc.
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*
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* Authors:
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* Sean Paul <seanpaul@chromium.org>
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*/
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#ifndef _DRM_HDCP_H_INCLUDED_
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#define _DRM_HDCP_H_INCLUDED_
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#include <linux/types.h>
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/* Period of hdcp checks (to ensure we're still authenticated) */
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#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
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#define DRM_HDCP2_CHECK_PERIOD_MS 500
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/* Shared lengths/masks between HDMI/DVI/DisplayPort */
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#define DRM_HDCP_AN_LEN 8
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#define DRM_HDCP_BSTATUS_LEN 2
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#define DRM_HDCP_KSV_LEN 5
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#define DRM_HDCP_RI_LEN 2
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#define DRM_HDCP_V_PRIME_PART_LEN 4
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#define DRM_HDCP_V_PRIME_NUM_PARTS 5
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#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
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#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
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#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
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/* Slave address for the HDCP registers in the receiver */
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#define DRM_HDCP_DDC_ADDR 0x3A
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/* Value to use at the end of the SHA-1 bytestream used for repeaters */
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#define DRM_HDCP_SHA1_TERMINATOR 0x80
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/* HDCP register offsets for HDMI/DVI devices */
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#define DRM_HDCP_DDC_BKSV 0x00
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#define DRM_HDCP_DDC_RI_PRIME 0x08
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#define DRM_HDCP_DDC_AKSV 0x10
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#define DRM_HDCP_DDC_AN 0x18
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#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
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#define DRM_HDCP_DDC_BCAPS 0x40
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#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
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#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
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#define DRM_HDCP_DDC_BSTATUS 0x41
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#define DRM_HDCP_DDC_KSV_FIFO 0x43
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#define DRM_HDCP_1_4_SRM_ID 0x8
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#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
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#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
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/* Protocol message definition for HDCP2.2 specification */
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/*
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* Protected content streams are classified into 2 types:
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* - Type0: Can be transmitted with HDCP 1.4+
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* - Type1: Can be transmitted with HDCP 2.2+
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*/
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#define HDCP_STREAM_TYPE0 0x00
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#define HDCP_STREAM_TYPE1 0x01
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/* HDCP2.2 Msg IDs */
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#define HDCP_2_2_NULL_MSG 1
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#define HDCP_2_2_AKE_INIT 2
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#define HDCP_2_2_AKE_SEND_CERT 3
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#define HDCP_2_2_AKE_NO_STORED_KM 4
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#define HDCP_2_2_AKE_STORED_KM 5
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#define HDCP_2_2_AKE_SEND_HPRIME 7
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#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8
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#define HDCP_2_2_LC_INIT 9
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#define HDCP_2_2_LC_SEND_LPRIME 10
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#define HDCP_2_2_SKE_SEND_EKS 11
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#define HDCP_2_2_REP_SEND_RECVID_LIST 12
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#define HDCP_2_2_REP_SEND_ACK 15
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#define HDCP_2_2_REP_STREAM_MANAGE 16
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#define HDCP_2_2_REP_STREAM_READY 17
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#define HDCP_2_2_RTX_LEN 8
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#define HDCP_2_2_RRX_LEN 8
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#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128
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#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3
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#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
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HDCP_2_2_K_PUB_RX_EXP_E_LEN)
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#define HDCP_2_2_DCP_LLC_SIG_LEN 384
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#define HDCP_2_2_E_KPUB_KM_LEN 128
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#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
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#define HDCP_2_2_H_PRIME_LEN 32
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#define HDCP_2_2_E_KH_KM_LEN 16
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#define HDCP_2_2_RN_LEN 8
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#define HDCP_2_2_L_PRIME_LEN 32
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#define HDCP_2_2_E_DKEY_KS_LEN 16
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#define HDCP_2_2_RIV_LEN 8
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#define HDCP_2_2_SEQ_NUM_LEN 3
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#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
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#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
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#define HDCP_2_2_MAX_DEVICE_COUNT 31
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#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \
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HDCP_2_2_MAX_DEVICE_COUNT)
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#define HDCP_2_2_MPRIME_LEN 32
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/* Following Macros take a byte at a time for bit(s) masking */
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/*
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* TODO: This has to be changed for DP MST, as multiple stream on
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* same port is possible.
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* For HDCP2.2 on HDMI and DP SST this value is always 1.
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*/
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#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
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#define HDCP_2_2_TXCAP_MASK_LEN 2
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#define HDCP_2_2_RXCAPS_LEN 3
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#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
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#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
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#define HDCP_2_2_RXINFO_LEN 2
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/* HDCP1.x compliant device in downstream */
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#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
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/* HDCP2.0 Compliant repeater in downstream */
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#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
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#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
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#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
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#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
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#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
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#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
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struct hdcp2_cert_rx {
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u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
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u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
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u8 reserved[2];
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u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
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} __packed;
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struct hdcp2_streamid_type {
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u8 stream_id;
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u8 stream_type;
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} __packed;
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/*
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* The TxCaps field specified in the HDCP HDMI, DP specs
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* This field is big endian as specified in the errata.
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*/
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struct hdcp2_tx_caps {
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/* Transmitter must set this to 0x2 */
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u8 version;
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/* Reserved for HDCP and DP Spec. Read as Zero */
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u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
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} __packed;
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/* Main structures for HDCP2.2 protocol communication */
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struct hdcp2_ake_init {
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u8 msg_id;
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u8 r_tx[HDCP_2_2_RTX_LEN];
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struct hdcp2_tx_caps tx_caps;
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} __packed;
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struct hdcp2_ake_send_cert {
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u8 msg_id;
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struct hdcp2_cert_rx cert_rx;
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u8 r_rx[HDCP_2_2_RRX_LEN];
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u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
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} __packed;
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struct hdcp2_ake_no_stored_km {
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u8 msg_id;
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u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
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} __packed;
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struct hdcp2_ake_stored_km {
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u8 msg_id;
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u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
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} __packed;
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struct hdcp2_ake_send_hprime {
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u8 msg_id;
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u8 h_prime[HDCP_2_2_H_PRIME_LEN];
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} __packed;
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struct hdcp2_ake_send_pairing_info {
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u8 msg_id;
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u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
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} __packed;
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struct hdcp2_lc_init {
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u8 msg_id;
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u8 r_n[HDCP_2_2_RN_LEN];
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} __packed;
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struct hdcp2_lc_send_lprime {
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u8 msg_id;
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u8 l_prime[HDCP_2_2_L_PRIME_LEN];
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} __packed;
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struct hdcp2_ske_send_eks {
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u8 msg_id;
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u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
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u8 riv[HDCP_2_2_RIV_LEN];
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} __packed;
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struct hdcp2_rep_send_receiverid_list {
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u8 msg_id;
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u8 rx_info[HDCP_2_2_RXINFO_LEN];
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u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
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u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
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u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
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} __packed;
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struct hdcp2_rep_send_ack {
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u8 msg_id;
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u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
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} __packed;
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struct hdcp2_rep_stream_manage {
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u8 msg_id;
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u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
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__be16 k;
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struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
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} __packed;
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struct hdcp2_rep_stream_ready {
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u8 msg_id;
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u8 m_prime[HDCP_2_2_MPRIME_LEN];
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} __packed;
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/* HDCP2.2 TIMEOUTs in mSec */
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#define HDCP_2_2_CERT_TIMEOUT_MS 100
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#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000
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#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200
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#define HDCP_2_2_PAIRING_TIMEOUT_MS 200
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#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20
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#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7
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#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000
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#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100
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/* HDMI HDCP2.2 Register Offsets */
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#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
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#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
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#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
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#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
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#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
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#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
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#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
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#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
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#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
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/* Below macros take a byte at a time and mask the bit(s) */
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#define HDCP_2_2_HDMI_RXSTATUS_LEN 2
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#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
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#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
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#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
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/*
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* Helper functions to convert 24bit big endian hdcp sequence number to
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* host format and back
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*/
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static inline
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u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])
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{
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return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16);
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}
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static inline
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void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)
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{
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seq_num[0] = val >> 16;
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seq_num[1] = val >> 8;
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seq_num[2] = val;
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}
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#define DRM_HDCP_SRM_GEN1_MAX_BYTES (5 * 1024)
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#define DRM_HDCP_1_4_SRM_ID 0x8
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#define DRM_HDCP_SRM_ID_MASK (0xF << 4)
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#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
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#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
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#define DRM_HDCP_2_SRM_ID 0x9
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#define DRM_HDCP_2_INDICATOR 0x1
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#define DRM_HDCP_2_INDICATOR_MASK 0xF
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#define DRM_HDCP_2_VRL_LENGTH_SIZE 3
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#define DRM_HDCP_2_DCP_SIG_SIZE 384
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#define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ 4
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#define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC0) >> 6)
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struct hdcp_srm_header {
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u8 srm_id;
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u8 reserved;
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__be16 srm_version;
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u8 srm_gen_no;
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} __packed;
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struct drm_device;
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struct drm_connector;
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int drm_hdcp_check_ksvs_revoked(struct drm_device *dev,
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u8 *ksvs, u32 ksv_count);
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int drm_connector_attach_content_protection_property(
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struct drm_connector *connector, bool hdcp_content_type);
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void drm_hdcp_update_content_protection(struct drm_connector *connector,
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u64 val);
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/* Content Type classification for HDCP2.2 vs others */
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#define DRM_MODE_HDCP_CONTENT_TYPE0 0
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#define DRM_MODE_HDCP_CONTENT_TYPE1 1
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#endif
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