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![Christoph Hellwig](/assets/img/avatar_default.png)
Drop the dma_direct_set_offset export and move the declaration to dma-map-ops.h now that the Allwinner drivers have stopped calling it. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
549 lines
15 KiB
C
549 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2020 Christoph Hellwig.
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*
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* DMA operations that map physical memory directly without using an IOMMU.
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*/
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#include <linux/memblock.h> /* for max_pfn */
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/dma-map-ops.h>
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#include <linux/scatterlist.h>
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#include <linux/pfn.h>
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#include <linux/vmalloc.h>
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#include <linux/set_memory.h>
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#include <linux/slab.h>
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#include "direct.h"
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/*
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* Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
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* it for entirely different regions. In that case the arch code needs to
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* override the variable below for dma-direct to work properly.
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*/
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unsigned int zone_dma_bits __ro_after_init = 24;
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static inline dma_addr_t phys_to_dma_direct(struct device *dev,
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phys_addr_t phys)
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{
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if (force_dma_unencrypted(dev))
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return phys_to_dma_unencrypted(dev, phys);
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return phys_to_dma(dev, phys);
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}
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static inline struct page *dma_direct_to_page(struct device *dev,
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dma_addr_t dma_addr)
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{
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return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
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}
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u64 dma_direct_get_required_mask(struct device *dev)
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{
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phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
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u64 max_dma = phys_to_dma_direct(dev, phys);
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return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
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}
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static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
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u64 *phys_limit)
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{
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u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
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/*
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* Optimistically try the zone that the physical address mask falls
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* into first. If that returns memory that isn't actually addressable
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* we will fallback to the next lower zone and try again.
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*
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* Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
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* zones.
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*/
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*phys_limit = dma_to_phys(dev, dma_limit);
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if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
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return GFP_DMA;
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if (*phys_limit <= DMA_BIT_MASK(32))
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return GFP_DMA32;
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return 0;
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}
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static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
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{
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dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
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if (dma_addr == DMA_MAPPING_ERROR)
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return false;
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return dma_addr + size - 1 <=
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min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
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}
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static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
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gfp_t gfp)
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{
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int node = dev_to_node(dev);
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struct page *page = NULL;
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u64 phys_limit;
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WARN_ON_ONCE(!PAGE_ALIGNED(size));
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gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
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&phys_limit);
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page = dma_alloc_contiguous(dev, size, gfp);
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if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
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dma_free_contiguous(dev, page, size);
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page = NULL;
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}
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again:
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if (!page)
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page = alloc_pages_node(node, gfp, get_order(size));
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if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
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dma_free_contiguous(dev, page, size);
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page = NULL;
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if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
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phys_limit < DMA_BIT_MASK(64) &&
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!(gfp & (GFP_DMA32 | GFP_DMA))) {
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gfp |= GFP_DMA32;
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goto again;
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}
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if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
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gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
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goto again;
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}
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}
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return page;
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}
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static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp)
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{
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struct page *page;
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u64 phys_mask;
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void *ret;
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gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
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&phys_mask);
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page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
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if (!page)
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return NULL;
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*dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
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return ret;
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}
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void *dma_direct_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
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{
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struct page *page;
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void *ret;
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int err;
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size = PAGE_ALIGN(size);
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if (attrs & DMA_ATTR_NO_WARN)
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gfp |= __GFP_NOWARN;
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if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
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!force_dma_unencrypted(dev)) {
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page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
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if (!page)
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return NULL;
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/* remove any dirty cache lines on the kernel alias */
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if (!PageHighMem(page))
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arch_dma_prep_coherent(page, size);
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*dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
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/* return the page pointer as the opaque cookie */
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return page;
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}
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if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
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!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
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!dev_is_dma_coherent(dev))
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return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
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/*
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* Remapping or decrypting memory may block. If either is required and
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* we can't block, allocate the memory from the atomic pools.
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*/
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if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
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!gfpflags_allow_blocking(gfp) &&
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(force_dma_unencrypted(dev) ||
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(IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev))))
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return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
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/* we always manually zero the memory once we are done */
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page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
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if (!page)
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return NULL;
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if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
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!dev_is_dma_coherent(dev)) ||
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(IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
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/* remove any dirty cache lines on the kernel alias */
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arch_dma_prep_coherent(page, size);
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/* create a coherent mapping */
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ret = dma_common_contiguous_remap(page, size,
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dma_pgprot(dev, PAGE_KERNEL, attrs),
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__builtin_return_address(0));
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if (!ret)
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goto out_free_pages;
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if (force_dma_unencrypted(dev)) {
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err = set_memory_decrypted((unsigned long)ret,
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1 << get_order(size));
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if (err)
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goto out_free_pages;
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}
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memset(ret, 0, size);
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goto done;
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}
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if (PageHighMem(page)) {
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/*
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* Depending on the cma= arguments and per-arch setup
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* dma_alloc_contiguous could return highmem pages.
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* Without remapping there is no way to return them here,
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* so log an error and fail.
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*/
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dev_info(dev, "Rejecting highmem page from CMA.\n");
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goto out_free_pages;
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}
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ret = page_address(page);
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if (force_dma_unencrypted(dev)) {
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err = set_memory_decrypted((unsigned long)ret,
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1 << get_order(size));
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if (err)
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goto out_free_pages;
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}
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memset(ret, 0, size);
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if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
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!dev_is_dma_coherent(dev)) {
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arch_dma_prep_coherent(page, size);
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ret = arch_dma_set_uncached(ret, size);
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if (IS_ERR(ret))
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goto out_encrypt_pages;
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}
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done:
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*dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
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return ret;
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out_encrypt_pages:
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if (force_dma_unencrypted(dev)) {
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err = set_memory_encrypted((unsigned long)page_address(page),
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1 << get_order(size));
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/* If memory cannot be re-encrypted, it must be leaked */
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if (err)
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return NULL;
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}
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out_free_pages:
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dma_free_contiguous(dev, page, size);
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return NULL;
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}
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void dma_direct_free(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
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{
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unsigned int page_order = get_order(size);
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if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
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!force_dma_unencrypted(dev)) {
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/* cpu_addr is a struct page cookie, not a kernel address */
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dma_free_contiguous(dev, cpu_addr, size);
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return;
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}
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if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
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!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
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!dev_is_dma_coherent(dev)) {
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arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
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return;
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}
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/* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
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if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
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dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
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return;
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if (force_dma_unencrypted(dev))
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set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
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if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
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vunmap(cpu_addr);
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else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
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arch_dma_clear_uncached(cpu_addr, size);
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dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
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}
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struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
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dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
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{
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struct page *page;
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void *ret;
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if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
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force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp))
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return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
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page = __dma_direct_alloc_pages(dev, size, gfp);
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if (!page)
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return NULL;
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if (PageHighMem(page)) {
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/*
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* Depending on the cma= arguments and per-arch setup
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* dma_alloc_contiguous could return highmem pages.
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* Without remapping there is no way to return them here,
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* so log an error and fail.
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*/
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dev_info(dev, "Rejecting highmem page from CMA.\n");
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goto out_free_pages;
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}
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ret = page_address(page);
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if (force_dma_unencrypted(dev)) {
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if (set_memory_decrypted((unsigned long)ret,
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1 << get_order(size)))
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goto out_free_pages;
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}
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memset(ret, 0, size);
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*dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
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return page;
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out_free_pages:
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dma_free_contiguous(dev, page, size);
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return NULL;
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}
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void dma_direct_free_pages(struct device *dev, size_t size,
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struct page *page, dma_addr_t dma_addr,
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enum dma_data_direction dir)
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{
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unsigned int page_order = get_order(size);
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void *vaddr = page_address(page);
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/* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
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if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
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dma_free_from_pool(dev, vaddr, size))
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return;
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if (force_dma_unencrypted(dev))
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set_memory_encrypted((unsigned long)vaddr, 1 << page_order);
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dma_free_contiguous(dev, page, size);
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}
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#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
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defined(CONFIG_SWIOTLB)
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void dma_direct_sync_sg_for_device(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i) {
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phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
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if (unlikely(is_swiotlb_buffer(paddr)))
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swiotlb_tbl_sync_single(dev, paddr, sg->length,
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dir, SYNC_FOR_DEVICE);
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if (!dev_is_dma_coherent(dev))
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arch_sync_dma_for_device(paddr, sg->length,
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dir);
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}
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}
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#endif
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#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
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defined(CONFIG_SWIOTLB)
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void dma_direct_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i) {
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phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
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if (!dev_is_dma_coherent(dev))
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arch_sync_dma_for_cpu(paddr, sg->length, dir);
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if (unlikely(is_swiotlb_buffer(paddr)))
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swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
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SYNC_FOR_CPU);
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if (dir == DMA_FROM_DEVICE)
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arch_dma_mark_clean(paddr, sg->length);
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}
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if (!dev_is_dma_coherent(dev))
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arch_sync_dma_for_cpu_all();
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}
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void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir, unsigned long attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
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attrs);
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}
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#endif
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int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
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enum dma_data_direction dir, unsigned long attrs)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sgl, sg, nents, i) {
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sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
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sg->offset, sg->length, dir, attrs);
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if (sg->dma_address == DMA_MAPPING_ERROR)
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goto out_unmap;
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sg_dma_len(sg) = sg->length;
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}
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return nents;
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out_unmap:
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dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
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return 0;
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}
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dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir, unsigned long attrs)
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{
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dma_addr_t dma_addr = paddr;
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if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
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dev_err_once(dev,
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"DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
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&dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
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WARN_ON_ONCE(1);
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return DMA_MAPPING_ERROR;
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}
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return dma_addr;
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}
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int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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struct page *page = dma_direct_to_page(dev, dma_addr);
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int ret;
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ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
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if (!ret)
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sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
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return ret;
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}
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bool dma_direct_can_mmap(struct device *dev)
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{
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return dev_is_dma_coherent(dev) ||
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IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
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}
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int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs)
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{
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unsigned long user_count = vma_pages(vma);
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unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
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int ret = -ENXIO;
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vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
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if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
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return ret;
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if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
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return -ENXIO;
|
|
return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
|
|
user_count << PAGE_SHIFT, vma->vm_page_prot);
|
|
}
|
|
|
|
int dma_direct_supported(struct device *dev, u64 mask)
|
|
{
|
|
u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
|
|
|
|
/*
|
|
* Because 32-bit DMA masks are so common we expect every architecture
|
|
* to be able to satisfy them - either by not supporting more physical
|
|
* memory, or by providing a ZONE_DMA32. If neither is the case, the
|
|
* architecture needs to use an IOMMU instead of the direct mapping.
|
|
*/
|
|
if (mask >= DMA_BIT_MASK(32))
|
|
return 1;
|
|
|
|
/*
|
|
* This check needs to be against the actual bit mask value, so use
|
|
* phys_to_dma_unencrypted() here so that the SME encryption mask isn't
|
|
* part of the check.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_ZONE_DMA))
|
|
min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
|
|
return mask >= phys_to_dma_unencrypted(dev, min_mask);
|
|
}
|
|
|
|
size_t dma_direct_max_mapping_size(struct device *dev)
|
|
{
|
|
/* If SWIOTLB is active, use its maximum mapping size */
|
|
if (is_swiotlb_active() &&
|
|
(dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
|
|
return swiotlb_max_mapping_size(dev);
|
|
return SIZE_MAX;
|
|
}
|
|
|
|
bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
|
|
{
|
|
return !dev_is_dma_coherent(dev) ||
|
|
is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
|
|
}
|
|
|
|
/**
|
|
* dma_direct_set_offset - Assign scalar offset for a single DMA range.
|
|
* @dev: device pointer; needed to "own" the alloced memory.
|
|
* @cpu_start: beginning of memory region covered by this offset.
|
|
* @dma_start: beginning of DMA/PCI region covered by this offset.
|
|
* @size: size of the region.
|
|
*
|
|
* This is for the simple case of a uniform offset which cannot
|
|
* be discovered by "dma-ranges".
|
|
*
|
|
* It returns -ENOMEM if out of memory, -EINVAL if a map
|
|
* already exists, 0 otherwise.
|
|
*
|
|
* Note: any call to this from a driver is a bug. The mapping needs
|
|
* to be described by the device tree or other firmware interfaces.
|
|
*/
|
|
int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
|
|
dma_addr_t dma_start, u64 size)
|
|
{
|
|
struct bus_dma_region *map;
|
|
u64 offset = (u64)cpu_start - (u64)dma_start;
|
|
|
|
if (dev->dma_range_map) {
|
|
dev_err(dev, "attempt to add DMA range to existing map\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!offset)
|
|
return 0;
|
|
|
|
map = kcalloc(2, sizeof(*map), GFP_KERNEL);
|
|
if (!map)
|
|
return -ENOMEM;
|
|
map[0].cpu_start = cpu_start;
|
|
map[0].dma_start = dma_start;
|
|
map[0].offset = offset;
|
|
map[0].size = size;
|
|
dev->dma_range_map = map;
|
|
return 0;
|
|
}
|