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9209fb5189
The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management. It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.
Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.
Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
17 lines
339 B
Makefile
17 lines
339 B
Makefile
# SPDX-License-Identifier: GPL-2.0-only
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CFLAGS_init.o := -mcmodel=medany
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ifdef CONFIG_FTRACE
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CFLAGS_REMOVE_init.o = -pg
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endif
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obj-y += init.o
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obj-y += extable.o
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obj-$(CONFIG_MMU) += fault.o
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obj-y += cacheflush.o
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obj-y += context.o
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ifeq ($(CONFIG_MMU),y)
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obj-$(CONFIG_SMP) += tlbflush.o
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endif
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obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
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