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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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3198a62eb8
Currently the VPU firmware prepares for D0i3 every time the VPU is entering D0i2 Idle state. This is not optimal as we might not enter D0i3 every time we enter D0i2 Idle and this preparation is quite costly. This optimization moves D0i3 preparation to a dedicated message sent from the host driver only when the driver is about to enter D0i3 - this reduces power consumption and latency for certain workloads, for example audio workloads that submit inference every 10 ms. The VPU needs non zero time to enter IDLE state after responding to D0i3 entry message. If the driver does not wait for the VPU to enter IDLE state it could cause warm boot failures. Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231028133415.1169975-12-stanislaw.gruszka@linux.intel.com
283 lines
9.5 KiB
C
283 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#include "ivpu_drv.h"
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#include "ivpu_hw.h"
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#include "ivpu_ipc.h"
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#include "ivpu_jsm_msg.h"
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const char *ivpu_jsm_msg_type_to_str(enum vpu_ipc_msg_type type)
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{
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#define IVPU_CASE_TO_STR(x) case x: return #x
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switch (type) {
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IVPU_CASE_TO_STR(VPU_JSM_MSG_UNKNOWN);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_RESET);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_PREEMPT);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_REGISTER_DB);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_UNREGISTER_DB);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_QUERY_ENGINE_HB);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL_COUNT);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_POWER_LEVEL);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_OPEN);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_CLOSE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_SET_CONFIG);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CONFIG);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CAPABILITY);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_NAME);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SSID_RELEASE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_START);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_STOP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_UPDATE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_INFO);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_CREATE_CMD_QUEUE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DESTROY_CMD_QUEUE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_REGISTER_DB);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_RESUME_CMDQ);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SUSPEND_CMDQ);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_RESUME_CMDQ_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SUSPEND_CMDQ_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SCHEDULING_LOG_NOTIFICATION);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_ENGINE_RESUME);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_RESUME_ENGINE_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_STATE_DUMP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_STATE_DUMP_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_BLOB_DEINIT);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DYNDBG_CONTROL);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_JOB_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_RESET_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_PREEMPT_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_REGISTER_DB_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_UNREGISTER_DB_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_QUERY_ENGINE_HB_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL_COUNT_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_POWER_LEVEL_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_OPEN_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_CLOSE_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_SET_CONFIG_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CONFIG_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CAPABILITY_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_NAME_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SSID_RELEASE_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_START_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_STOP_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_UPDATE_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_INFO_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_NOTIFICATION);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_CREATE_CMD_QUEUE_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DESTROY_CMD_QUEUE_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_BLOB_DEINIT_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DYNDBG_CONTROL_RSP);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_PWR_D0I3_ENTER);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_PWR_D0I3_ENTER_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_ENABLE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_ENABLE_DONE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_DISABLE);
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IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_DISABLE_DONE);
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}
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#undef IVPU_CASE_TO_STR
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return "Unknown JSM message type";
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}
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int ivpu_jsm_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 db_id,
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u64 jobq_base, u32 jobq_size)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_REGISTER_DB };
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struct vpu_jsm_msg resp;
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int ret = 0;
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req.payload.register_db.db_idx = db_id;
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req.payload.register_db.jobq_base = jobq_base;
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req.payload.register_db.jobq_size = jobq_size;
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req.payload.register_db.host_ssid = ctx_id;
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret) {
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ivpu_err_ratelimited(vdev, "Failed to register doorbell %d: %d\n", db_id, ret);
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return ret;
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}
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ivpu_dbg(vdev, JSM, "Doorbell %d registered to context %d\n", db_id, ctx_id);
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return 0;
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}
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int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_UNREGISTER_DB };
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struct vpu_jsm_msg resp;
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int ret = 0;
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req.payload.unregister_db.db_idx = db_id;
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_UNREGISTER_DB_DONE, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret) {
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ivpu_warn_ratelimited(vdev, "Failed to unregister doorbell %d: %d\n", db_id, ret);
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return ret;
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}
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ivpu_dbg(vdev, JSM, "Doorbell %d unregistered\n", db_id);
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return 0;
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}
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int ivpu_jsm_get_heartbeat(struct ivpu_device *vdev, u32 engine, u64 *heartbeat)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB };
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struct vpu_jsm_msg resp;
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int ret;
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if (engine > VPU_ENGINE_COPY)
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return -EINVAL;
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req.payload.query_engine_hb.engine_idx = engine;
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret) {
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ivpu_err_ratelimited(vdev, "Failed to get heartbeat from engine %d: %d\n",
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engine, ret);
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return ret;
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}
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*heartbeat = resp.payload.query_engine_hb_done.heartbeat;
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return ret;
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}
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int ivpu_jsm_reset_engine(struct ivpu_device *vdev, u32 engine)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_ENGINE_RESET };
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struct vpu_jsm_msg resp;
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int ret;
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if (engine > VPU_ENGINE_COPY)
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return -EINVAL;
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req.payload.engine_reset.engine_idx = engine;
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_ENGINE_RESET_DONE, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret)
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ivpu_err_ratelimited(vdev, "Failed to reset engine %d: %d\n", engine, ret);
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return ret;
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}
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int ivpu_jsm_preempt_engine(struct ivpu_device *vdev, u32 engine, u32 preempt_id)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_ENGINE_PREEMPT };
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struct vpu_jsm_msg resp;
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int ret;
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if (engine > VPU_ENGINE_COPY)
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return -EINVAL;
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req.payload.engine_preempt.engine_idx = engine;
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req.payload.engine_preempt.preempt_id = preempt_id;
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_ENGINE_PREEMPT_DONE, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret)
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ivpu_err_ratelimited(vdev, "Failed to preempt engine %d: %d\n", engine, ret);
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return ret;
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}
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int ivpu_jsm_dyndbg_control(struct ivpu_device *vdev, char *command, size_t size)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DYNDBG_CONTROL };
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struct vpu_jsm_msg resp;
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int ret;
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strscpy(req.payload.dyndbg_control.dyndbg_cmd, command, VPU_DYNDBG_CMD_MAX_LEN);
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_DYNDBG_CONTROL_RSP, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret)
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ivpu_warn_ratelimited(vdev, "Failed to send command \"%s\": ret %d\n",
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command, ret);
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return ret;
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}
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int ivpu_jsm_trace_get_capability(struct ivpu_device *vdev, u32 *trace_destination_mask,
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u64 *trace_hw_component_mask)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_TRACE_GET_CAPABILITY };
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struct vpu_jsm_msg resp;
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int ret;
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_TRACE_GET_CAPABILITY_RSP, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret) {
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ivpu_warn_ratelimited(vdev, "Failed to get trace capability: %d\n", ret);
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return ret;
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}
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*trace_destination_mask = resp.payload.trace_capability.trace_destination_mask;
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*trace_hw_component_mask = resp.payload.trace_capability.trace_hw_component_mask;
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return ret;
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}
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int ivpu_jsm_trace_set_config(struct ivpu_device *vdev, u32 trace_level, u32 trace_destination_mask,
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u64 trace_hw_component_mask)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_TRACE_SET_CONFIG };
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struct vpu_jsm_msg resp;
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int ret;
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req.payload.trace_config.trace_level = trace_level;
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req.payload.trace_config.trace_destination_mask = trace_destination_mask;
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req.payload.trace_config.trace_hw_component_mask = trace_hw_component_mask;
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ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_TRACE_SET_CONFIG_RSP, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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if (ret)
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ivpu_warn_ratelimited(vdev, "Failed to set config: %d\n", ret);
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return ret;
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}
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int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SSID_RELEASE };
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struct vpu_jsm_msg resp;
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req.payload.ssid_release.host_ssid = host_ssid;
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return ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SSID_RELEASE_DONE, &resp,
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VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
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}
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int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev)
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{
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struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_PWR_D0I3_ENTER };
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struct vpu_jsm_msg resp;
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int ret;
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if (IVPU_WA(disable_d0i3_msg))
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return 0;
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req.payload.pwr_d0i3_enter.send_response = 1;
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ret = ivpu_ipc_send_receive_active(vdev, &req, VPU_JSM_MSG_PWR_D0I3_ENTER_DONE,
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&resp, VPU_IPC_CHAN_GEN_CMD,
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vdev->timeout.d0i3_entry_msg);
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if (ret)
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return ret;
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return ivpu_hw_wait_for_idle(vdev);
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}
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