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![Krystian Pradzynski](/assets/img/avatar_default.png)
Bump boot API to 4.20 Bump JSM API to 3.15 Signed-off-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231028133415.1169975-2-stanislaw.gruszka@linux.intel.com
421 lines
14 KiB
C
421 lines
14 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#ifndef VPU_BOOT_API_H
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#define VPU_BOOT_API_H
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/*
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* =========== FW API version information beginning ================
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* The bellow values will be used to construct the version info this way:
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* fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
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* VPU_BOOT_API_VER_MINOR;
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* VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes
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* This information is collected by using vpuip_2/application/vpuFirmware/make_std_fw_image.py
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* If a header is missing this info we ignore the header, if a header is missing or contains
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* partial info a build error will be generated.
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*/
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/*
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* Major version changes that break backward compatibility.
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* Major version must start from 1 and can only be incremented.
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*/
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#define VPU_BOOT_API_VER_MAJOR 3
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/*
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* Minor version changes when API backward compatibility is preserved.
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* Resets to 0 if Major version is incremented.
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*/
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#define VPU_BOOT_API_VER_MINOR 20
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/*
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* API header changed (field names, documentation, formatting) but API itself has not been changed
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*/
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#define VPU_BOOT_API_VER_PATCH 4
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/*
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* Index in the API version table
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* Must be unique for each API
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*/
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#define VPU_BOOT_API_VER_INDEX 0
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/* ------------ FW API version information end ---------------------*/
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#pragma pack(push, 1)
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/*
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* Firmware image header format
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*/
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#define VPU_FW_HEADER_SIZE 4096
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#define VPU_FW_HEADER_VERSION 0x1
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#define VPU_FW_VERSION_SIZE 32
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#define VPU_FW_API_VER_NUM 16
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struct vpu_firmware_header {
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u32 header_version;
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u32 image_format;
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u64 image_load_address;
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u32 image_size;
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u64 entry_point;
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u8 vpu_version[VPU_FW_VERSION_SIZE];
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u32 compression_type;
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u64 firmware_version_load_address;
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u32 firmware_version_size;
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u64 boot_params_load_address;
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u32 api_version[VPU_FW_API_VER_NUM];
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/* Size of memory require for firmware execution */
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u32 runtime_size;
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u32 shave_nn_fw_size;
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/* Size of primary preemption buffer. */
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u32 preemption_buffer_1_size;
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/* Size of secondary preemption buffer. */
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u32 preemption_buffer_2_size;
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/* Space reserved for future preemption-related fields. */
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u32 preemption_reserved[6];
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};
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/*
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* Firmware boot parameters format
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*/
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#define VPU_BOOT_PLL_COUNT 3
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#define VPU_BOOT_PLL_OUT_COUNT 4
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/** Values for boot_type field */
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#define VPU_BOOT_TYPE_COLDBOOT 0
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#define VPU_BOOT_TYPE_WARMBOOT 1
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/** Value for magic filed */
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#define VPU_BOOT_PARAMS_MAGIC 0x10000
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/** VPU scheduling mode. By default, OS scheduling is used. */
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#define VPU_SCHEDULING_MODE_OS 0
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#define VPU_SCHEDULING_MODE_HW 1
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enum VPU_BOOT_L2_CACHE_CFG_TYPE {
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VPU_BOOT_L2_CACHE_CFG_UPA = 0,
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VPU_BOOT_L2_CACHE_CFG_NN = 1,
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VPU_BOOT_L2_CACHE_CFG_NUM = 2
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};
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/** VPU MCA ECC signalling mode. By default, no signalling is used */
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enum VPU_BOOT_MCA_ECC_SIGNAL_TYPE {
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VPU_BOOT_MCA_ECC_NONE = 0,
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VPU_BOOT_MCA_ECC_CORR = 1,
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VPU_BOOT_MCA_ECC_FATAL = 2,
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VPU_BOOT_MCA_ECC_BOTH = 3
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};
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/**
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* Logging destinations.
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*
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* Logging output can be directed to different logging destinations. This enum
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* defines the list of logging destinations supported by the VPU firmware (NOTE:
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* a specific VPU FW binary may support only a subset of such output
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* destinations, depending on the target platform and compile options).
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*/
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enum vpu_trace_destination {
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VPU_TRACE_DESTINATION_PIPEPRINT = 0x1,
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VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2,
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VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4,
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};
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/*
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* Processor bit shifts (for loggable HW components).
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*/
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#define VPU_TRACE_PROC_BIT_ARM 0
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#define VPU_TRACE_PROC_BIT_LRT 1
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#define VPU_TRACE_PROC_BIT_LNN 2
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#define VPU_TRACE_PROC_BIT_SHV_0 3
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#define VPU_TRACE_PROC_BIT_SHV_1 4
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#define VPU_TRACE_PROC_BIT_SHV_2 5
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#define VPU_TRACE_PROC_BIT_SHV_3 6
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#define VPU_TRACE_PROC_BIT_SHV_4 7
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#define VPU_TRACE_PROC_BIT_SHV_5 8
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#define VPU_TRACE_PROC_BIT_SHV_6 9
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#define VPU_TRACE_PROC_BIT_SHV_7 10
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#define VPU_TRACE_PROC_BIT_SHV_8 11
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#define VPU_TRACE_PROC_BIT_SHV_9 12
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#define VPU_TRACE_PROC_BIT_SHV_10 13
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#define VPU_TRACE_PROC_BIT_SHV_11 14
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#define VPU_TRACE_PROC_BIT_SHV_12 15
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#define VPU_TRACE_PROC_BIT_SHV_13 16
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#define VPU_TRACE_PROC_BIT_SHV_14 17
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#define VPU_TRACE_PROC_BIT_SHV_15 18
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#define VPU_TRACE_PROC_BIT_ACT_SHV_0 19
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#define VPU_TRACE_PROC_BIT_ACT_SHV_1 20
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#define VPU_TRACE_PROC_BIT_ACT_SHV_2 21
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#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22
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#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23
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/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
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#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
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#define VPU_TRACE_PROC_BIT_30XX_LAST VPU_TRACE_PROC_BIT_SHV_15
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#define VPU_TRACE_PROC_BIT_KMB_FIRST VPU_TRACE_PROC_BIT_30XX_FIRST
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#define VPU_TRACE_PROC_BIT_KMB_LAST VPU_TRACE_PROC_BIT_30XX_LAST
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struct vpu_boot_l2_cache_config {
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u8 use;
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u8 cfg;
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};
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struct vpu_warm_boot_section {
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u32 src;
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u32 dst;
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u32 size;
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u32 core_id;
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u32 is_clear_op;
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};
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/*
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* When HW scheduling mode is enabled, a present period is defined.
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* It will be used by VPU to swap between normal and focus priorities
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* to prevent starving of normal priority band (when implemented).
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* Host must provide a valid value at boot time in
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* `vpu_focus_present_timer_ms`. If the value provided by the host is not within the
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* defined range a default value will be used. Here we define the min. and max.
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* allowed values and the and default value of the present period. Units are milliseconds.
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*/
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#define VPU_PRESENT_CALL_PERIOD_MS_DEFAULT 50
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#define VPU_PRESENT_CALL_PERIOD_MS_MIN 16
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#define VPU_PRESENT_CALL_PERIOD_MS_MAX 10000
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/**
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* Macros to enable various operation modes within the VPU.
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* To be defined as part of 32 bit mask.
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*/
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#define VPU_OP_MODE_SURVIVABILITY 0x1
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struct vpu_boot_params {
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u32 magic;
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u32 vpu_id;
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u32 vpu_count;
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u32 pad0[5];
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/* Clock frequencies: 0x20 - 0xFF */
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u32 frequency;
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u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
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u32 perf_clk_frequency;
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u32 pad1[42];
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/* Memory regions: 0x100 - 0x1FF */
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u64 ipc_header_area_start;
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u32 ipc_header_area_size;
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u64 shared_region_base;
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u32 shared_region_size;
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u64 ipc_payload_area_start;
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u32 ipc_payload_area_size;
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u64 global_aliased_pio_base;
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u32 global_aliased_pio_size;
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u32 autoconfig;
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struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];
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u64 global_memory_allocator_base;
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u32 global_memory_allocator_size;
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/**
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* ShaveNN FW section VPU base address
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* On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base
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*/
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u64 shave_nn_fw_base;
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u64 save_restore_ret_address; /* stores the address of FW's restore entry point */
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u32 pad2[43];
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/* IRQ re-direct numbers: 0x200 - 0x2FF */
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s32 watchdog_irq_mss;
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s32 watchdog_irq_nce;
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/* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
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u32 host_to_vpu_irq;
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/* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
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u32 job_done_irq;
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/* VPU -> ARM IRQ line to use to request MMU update. */
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u32 mmu_update_request_irq;
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/* ARM -> VPU IRQ line to use to notify of MMU update completion. */
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u32 mmu_update_done_irq;
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/* ARM -> VPU IRQ line to use to request power level change. */
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u32 set_power_level_irq;
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/* VPU -> ARM IRQ line to use to notify of power level change completion. */
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u32 set_power_level_done_irq;
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/* VPU -> ARM IRQ line to use to notify of VPU idle state change */
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u32 set_vpu_idle_update_irq;
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/* VPU -> ARM IRQ line to use to request counter reset. */
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u32 metric_query_event_irq;
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/* ARM -> VPU IRQ line to use to notify of counter reset completion. */
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u32 metric_query_event_done_irq;
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/* VPU -> ARM IRQ line to use to notify of preemption completion. */
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u32 preemption_done_irq;
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/* Padding. */
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u32 pad3[52];
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/* Silicon information: 0x300 - 0x3FF */
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u32 host_version_id;
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u32 si_stepping;
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u64 device_id;
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u64 feature_exclusion;
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u64 sku;
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/** PLL ratio for minimum clock frequency */
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u32 min_freq_pll_ratio;
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/** PLL ratio for maximum clock frequency */
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u32 max_freq_pll_ratio;
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/**
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* Initial log level threshold (messages with log level severity less than
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* the threshold will not be logged); applies to every enabled logging
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* destination and loggable HW component. See 'mvLog_t' enum for acceptable
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* values.
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* TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
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*/
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u32 default_trace_level;
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u32 boot_type;
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u64 punit_telemetry_sram_base;
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u64 punit_telemetry_sram_size;
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u32 vpu_telemetry_enable;
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u64 crit_tracing_buff_addr;
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u32 crit_tracing_buff_size;
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u64 verbose_tracing_buff_addr;
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u32 verbose_tracing_buff_size;
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u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */
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/**
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* Mask of destinations to which logging messages are delivered; bitwise OR
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* of values defined in vpu_trace_destination enum.
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*/
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u32 trace_destination_mask;
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/**
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* Mask of hardware components for which logging is enabled; bitwise OR of
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* bits defined by the VPU_TRACE_PROC_BIT_* macros.
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*/
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u64 trace_hw_component_mask;
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/** Mask of trace message formats supported by the driver */
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u64 tracing_buff_message_format_mask;
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u64 trace_reserved_1[2];
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/**
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* Period at which the VPU reads the temp sensor values into MMIO, on
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* platforms where that is necessary (in ms). 0 to disable reads.
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*/
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u32 temp_sensor_period_ms;
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/** PLL ratio for efficient clock frequency */
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u32 pn_freq_pll_ratio;
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/** DVFS Mode: Default: 0, Max Performance: 1, On Demand: 2, Power Save: 3 */
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u32 dvfs_mode;
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/**
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* Depending on DVFS Mode:
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* On-demand: Default if 0.
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* Bit 0-7 - uint8_t: Highest residency percent
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* Bit 8-15 - uint8_t: High residency percent
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* Bit 16-23 - uint8_t: Low residency percent
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* Bit 24-31 - uint8_t: Lowest residency percent
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* Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
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* Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
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* Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
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* Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
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* Bit 48-55 - uint8_t: Period (ms) for residency decisions
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* Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
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* Power Save/Max Performance: Unused
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*/
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u64 dvfs_param;
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/**
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* D0i3 delayed entry
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* Bit0: Disable CPU state save on D0i2 entry flow.
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* 0: Every D0i2 entry saves state. Save state IPC message ignored.
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* 1: IPC message required to save state on D0i3 entry flow.
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*/
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u32 d0i3_delayed_entry;
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/* Time spent by VPU in D0i3 state */
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u64 d0i3_residency_time_us;
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/* Value of VPU perf counter at the time of entering D0i3 state . */
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u64 d0i3_entry_vpu_ts;
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u32 pad4[20];
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/* Warm boot information: 0x400 - 0x43F */
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u32 warm_boot_sections_count;
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u32 warm_boot_start_address_reference;
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u32 warm_boot_section_info_address_offset;
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u32 pad5[13];
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/* Power States transitions timestamps: 0x440 - 0x46F*/
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struct {
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/* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
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u64 vpu_active_state_requested;
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/* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
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u64 vpu_active_state_achieved;
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/* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
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u64 vpu_idle_state_requested;
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/* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
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u64 vpu_idle_state_achieved;
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/* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
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u64 vpu_standby_state_requested;
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/* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
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u64 vpu_standby_state_achieved;
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} power_states_timestamps;
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/* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
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u32 vpu_scheduling_mode;
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/* Present call period in milliseconds. */
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u32 vpu_focus_present_timer_ms;
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/* VPU ECC Signaling */
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u32 vpu_uses_ecc_mca_signal;
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/* Values defined by VPU_OP_MODE* macros */
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u32 vpu_operation_mode;
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/* Unused/reserved: 0x480 - 0xFFF */
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u32 pad6[736];
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};
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/*
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* Magic numbers set between host and vpu to detect corruptio of tracing init
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*/
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#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)
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/* Tracing buffer message format definitions */
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#define VPU_TRACING_FORMAT_STRING 0
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#define VPU_TRACING_FORMAT_MIPI 2
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/*
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* Header of the tracing buffer.
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* The below defined header will be stored at the beginning of
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* each allocated tracing buffer, followed by a series of 256b
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* of ASCII trace message entries.
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*/
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struct vpu_tracing_buffer_header {
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/**
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* Magic number set by host to detect corruption
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* @see VPU_TRACING_BUFFER_CANARY
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*/
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u32 host_canary_start;
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/* offset from start of buffer for trace entries */
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u32 read_index;
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u32 pad_to_cache_line_size_0[14];
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/* End of first cache line */
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/**
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* Magic number set by host to detect corruption
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* @see VPU_TRACING_BUFFER_CANARY
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*/
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u32 vpu_canary_start;
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/* offset from start of buffer from write start */
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u32 write_index;
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/* counter for buffer wrapping */
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u32 wrap_count;
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/* legacy field - do not use */
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u32 reserved_0;
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/**
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* Size of the log buffer include this header (@header_size) and space
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* reserved for all messages. If @alignment` is greater that 0 the @Size
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* must be multiple of @Alignment.
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*/
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u32 size;
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/* Header version */
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u16 header_version;
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/* Header size */
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u16 header_size;
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/*
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* Format of the messages in the trace buffer
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* 0 - null terminated string
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* 1 - size + null terminated string
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* 2 - MIPI-SysT encoding
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*/
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u32 format;
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/*
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* Message alignment
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* 0 - messages are place 1 after another
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* n - every message starts and multiple on offset
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*/
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u32 alignment; /* 64, 128, 256 */
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/* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
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char name[16];
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u32 pad_to_cache_line_size_1[4];
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/* End of second cache line */
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};
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#pragma pack(pop)
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#endif
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