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fa466c9197
Currently the pre-scaler limit is incorrect. The value differs slightly for various devices so a single value can't be used. Using the compatible field select the correct pre-scaler limit. Add new compatible field value for Keystone devices to support their unique pre-scaler limit value. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
90 lines
3.1 KiB
C
90 lines
3.1 KiB
C
/*
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* Copyright 2009 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ARCH_ARM_DAVINCI_SPI_H
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#define __ARCH_ARM_DAVINCI_SPI_H
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#include <linux/platform_data/edma.h>
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#define SPI_INTERN_CS 0xFF
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enum {
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SPI_VERSION_1, /* For DM355/DM365/DM6467 */
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SPI_VERSION_2, /* For DA8xx */
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};
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/**
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* davinci_spi_platform_data - Platform data for SPI master device on DaVinci
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*
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* @version: version of the SPI IP. Different DaVinci devices have slightly
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* varying versions of the same IP.
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* @num_chipselect: number of chipselects supported by this SPI master
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* @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt
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* controller withn the SoC. Possible values are 0 and 1.
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* @chip_sel: list of GPIOs which can act as chip-selects for the SPI.
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* SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
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* to populate if all chip-selects are internal.
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* @cshold_bug: set this to true if the SPI controller on your chip requires
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* a write to CSHOLD bit in between transfers (like in DM355).
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* @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
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* device on the bus.
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*/
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struct davinci_spi_platform_data {
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u8 version;
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u8 num_chipselect;
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u8 intr_line;
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u8 *chip_sel;
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u8 prescaler_limit;
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bool cshold_bug;
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enum dma_event_q dma_event_q;
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};
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/**
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* davinci_spi_config - Per-chip-select configuration for SPI slave devices
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*
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* @wdelay: amount of delay between transmissions. Measured in number of
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* SPI module clocks.
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* @odd_parity: polarity of parity flag at the end of transmit data stream.
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* 0 - odd parity, 1 - even parity.
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* @parity_enable: enable transmission of parity at end of each transmit
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* data stream.
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* @io_type: type of IO transfer. Choose between polled, interrupt and DMA.
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* @timer_disable: disable chip-select timers (setup and hold)
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* @c2tdelay: chip-select setup time. Measured in number of SPI module clocks.
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* @t2cdelay: chip-select hold time. Measured in number of SPI module clocks.
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* @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured
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* in number of SPI clocks.
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* @c2edelay: chip-select active to SPI ENAn signal active time. Measured in
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* number of SPI clocks.
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*/
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struct davinci_spi_config {
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u8 wdelay;
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u8 odd_parity;
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u8 parity_enable;
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#define SPI_IO_TYPE_INTR 0
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#define SPI_IO_TYPE_POLL 1
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#define SPI_IO_TYPE_DMA 2
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u8 io_type;
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u8 timer_disable;
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u8 c2tdelay;
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u8 t2cdelay;
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u8 t2edelay;
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u8 c2edelay;
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};
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#endif /* __ARCH_ARM_DAVINCI_SPI_H */
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